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2010 | Buch

Market and applications for NAND Flash memories Kapitel lesen Erstes Kapitel lesen

Inside NAND Flash Memories

verfasst von: Rino Micheloni, Luca Crippa, Alessia Marelli

Verlag: Springer Netherlands

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

Digital photography, MP3, digital video, etc. make extensive use of NAND-based Flash cards as storage media. To realize how much NAND Flash memories pervade every aspect of our life, just imagine how our recent habits would change if the NAND memories suddenly disappeared. To take a picture it would be necessary to find a film (as well as a traditional camera…), disks or even magnetic tapes would be used to record a video or to listen a song, and a cellular phone would return to be a simple mean of communication rather than a multimedia console. The development of NAND Flash memories will not be set down on the mere evolution of personal entertainment systems since a new killer application can trigger a further success: the replacement of Hard Disk Drives (HDDs) with Solid State Drives (SSDs). SSD is made up by a microcontroller and several NANDs. As NAND is the technology driver for IC circuits, Flash designers and technologists have to deal with a lot of challenges. Therefore, SSD (system) developers must understand Flash technology in order to exploit its benefits and countermeasure its weaknesses. Inside NAND Flash Memories is a comprehensive guide of the NAND world: from circuits design (analog and digital) to Flash reliability (including radiation effects), from testing issues to high-performance (DDR) interface, from error correction codes to NAND applications like Flash cards and SSDs.

Inhaltsverzeichnis

Frontmatter
1. Market and applications for NAND Flash memories
Abstract
In the year 2000, the total semiconductor memory revenues of SRAM, DRAM, 6 NOR Flash and NAND Flash memories amounted $46 billion. As the decade 7 closed in 2009, total revenues are projected to have declined 8.7% to $42 billion. 8 Of the major memory segments, only NAND Flash memory revenues have grown 9 in the past decade at a CAGR of almost 50% (see Fig. 1.1).
Gregory Wong
2. NAND overview: from memory to systems
Abstract
It was in 1965, just after the invention of the bipolar transistor by W. Shockley, W. Brattain and J. Bardeen, that Gordon Moore, co-founder of Intel, observed that the number of transistors per square centimeter in a microchip doubled every year. Moore thought that such trend would have proven true for the years to come as well, and indeed in the following years the density of active components in an integrated circuit kept on doubling every 18 months. For example, in the 18 months that elapsed between the Pentium processor 1.3 and the Pentium-4, the number of transistors grew from 28 to 55 million.
R. Micheloni, A. Marelli, S. Commodaro
3. Program and erase of NAND memory arrays
Abstract
The purpose of NAND Flash memories as a non-volatile memory is to store the user data for years without requiring a supply voltage. The state of the art memory cell for this purpose in NAND Flash is the 1T floating gate memory cell, which is based on a MOSFET. In contrast to the 1T1C DRAM cell, which consists of an access transistor and a separate capacitance as charge storage node, the 1T floating gate cell is a MOSFET whose gate dielectric is split with a charge storage node in between. This charge storing node, usually made of poly-silicon, is electrically isolated completely by the surrounding dielectrics. Its stored charges represent the information, and may be altered according to the user data by the program operation.
Christoph Friederich
4. Reliability issues of NAND Flash memories
Abstract
The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view.
C. Zambelli, A. Chimenton, P. Olivo
5. Charge trap NAND technologies
Abstract
In the last years a big research effort has been spent in the study of new technologies that could represent a possible alternative to conventional floating gate (FG) NAND. In fact even if FG NAND is the dominant technology and there is no advice of reduction in scaling pace, several physical roadblocks seem to limit future scalability (e.g. electrostatic interference among adjacent cells). Charge trap (CT) memories may overcome some of these limitations and represent the best candidate to substitute FG devices for future nodes [1]. Differently from floating gate cells that have a semiconductor as storage element, in CT case electrons are trapped inside a dielectric layer. The different storage material change drastically cell architecture impacting also on physical mechanisms for write operations (both program and erase) and reliability.
Alessandro Grossi
6. Control logic
Abstract
Logic is the part of the NAND device that enables the communication with the external user and organizes data inside the device and the functionalities of the device itself. It represents the interface with the user and the brain of the device.
A. Marelli, R. Micheloni, R. Ravasio
7. NAND DDR interface
Abstract
Nowadays NAND Flash memory is pervading every type of electronic application. The availability of cheap storage memory, in combination with high densities, makes up the choice in favor of NAND Flash on board of applications traditionally linked to other types of memories (such as EEPROM and NOR) or technologies (such as Hard Disk Drives). Mobile devices, PDA, PC, camcorders, set top boxes, servers, routers, enterprise storage and many more new applications requiring a storage media will have to deal with NAND Flash in the coming years. The memories environment has changed since year 2001 when growth rate for NAND surpassed the ‘Moore law’ observed for processor growth and predicting a double density every eighteen months. By then, NAND devices with double density have been introduced every year. In addition, MLC devices with 2 bit/cell entered volume production.
Andrea Silvagni
8. Sensing circuits
Abstract
The reading operation is designed to address a memory cell and extrapolate the information stored therein. In the case of a NAND-type Flash memory, the memory cells are connected in series, in groups (strings) of 2k cells, up to 64.
L. Crippa, R. Micheloni
9. Parasitic effects and verify circuits
Abstract
As anticipated in the introduction to Chap. 8, the current–voltage (I/V) characteristic 5 of the cell is influenced by the data being programmed afterwards in the other 6 cells. In order to avoid the source degeneration effect (load variation between cell 7 source terminal and SL), the cells of a string are sequentially programmed starting 8 from the source-side cell all the way to the bitline-side cell. For instance (Fig. 9.1), 9 cell M0 is programmed first, followed by M1, M2 and so on. The drain-side load 10 variation has a “modulation” effect on the I/V characteristic of the cell in terms of 11 both reduction of the saturation current ISSAT and variation of the slope (Fig. 8.3). 12 Such a modulation effect is known as Background Pattern Dependency (BPD). 13 The physical threshold voltage of M0, VTH, obviously does not change (neglecting 14 the floating gate coupling effect M1 - M0).
L. Crippa, R. Micheloni
10. MLC storage
Abstract
The obvious advantage of a 2 bit/cell implementation (MLC) with respect to a 1 bit/cell device (SLC) is that the area occupation of the matrix is half as much; on the other hand, the area of the periphery circuits, both analog and digital, increases. This is mainly due to the fact that the multilevel approach requires higher voltages for program (and therefore bigger charge pumps), higher precision and better performance in the generation of both the analog signals and the timings, and an increase in the complexity of the algorithms.
L. Crippa, R. Micheloni
11. Charge pumps, voltage regulators and HV switches
Abstract
Modifying or reading the number of electrons stored into the floating gate requires a big set of voltages. The high voltage (HV) system has to provide all these voltages with the desired precision, timing and granularity. On top of that, many voltages have a value greater than the NAND power supply VDD, asking for an on-chip charge pump. This chapter deals with the HV basic building blocks.
R. Micheloni, L. Crippa
12. High voltage overview
Abstract
Program and erase are the only two operations able to modify the content of the cells. Since the content of the cells is strictly related to the number ν of electrons inside the floating gate, these operations involve high electric fields (i.e. high voltages) to exploit the Fowler-Nordheim phenomena (Chap. 3 and change ν. Particular attention must be taken when dealing with high voltages, since a little variation could have dramatic consequences.
R. Micheloni, A. Marelli
13. Redundancy
Abstract
Redundancy is part of the NAND circuits which take care of its reliability. In addition to redundancy, modern NAND Flash use error correction codes to improve device reliability.
A. Marelli, R. Micheloni
14. Error correction codes
Abstract
As we have seen in Chap. 13, redundancy covers manufacturing defects while ECC takes care of the failures during the life of the device. This chapter deals with error correction codes applied to NAND Flash memories. In fact, when the memory is placed in its final application, different reasons for errors (see Chap. 4) can damage the written information so that it could happen that the read message is not equal to the original anymore [1].
T. Zhang, A. Marelli, R. Micheloni
15. NAND design for testability and testing
Abstract
NAND business requires huge investments in technology developments and manufacturing. Moreover, leading edge NAND Flash memory costs and yield issues increase with every new technology node. Addressing test issues is mandatory for NAND Flash manufacturers to accelerate yield learning and enhancement, maintaining a competitive cost structure.
Andrea Silvagni
16. XLC storage
Abstract
The obvious advantage of designing NAND devices capable of storing n-bit/cell (where n is currently 2, 3, and 4) is the resulting reduction in area occupation of the matrix. However, the benefits of 3-bit/cell (or 8-Level-Cell, 8LC) and 4-bit/cell (or 16-Level-Cell, 16LC) technologies don’t come for free.
R. Micheloni, L. Crippa
17. Flash cards
Abstract
Memory cards are solid-state devices engineered to store digital information. They come in several forms and shapes but nonetheless they have many common characteristics. In this chapter, we will describe memory cards from a user standpoint, their internal architecture and the algorithms operating within, the difficulties with relevant counter-stratagems inherent in their design.
A. Ghilardelli, S. Corno
18. Low power 3D-integrated SSD
Abstract
With highly scaled 40 or 30 nm technologies, the memory capacity increases to as much as 32 Gbit as shown in Fig. 18.1. By using gigabit-capacity NAND flash memories, SSD, Solid-State Drive that uses NAND as a mass storage of personal computers and enterprise servers is expected as a next killer application of NAND Flash memories.
K. Takeuchi
19. Radiation effects on NAND Flash memories
Abstract
Electronic chips operating at sea level are constantly bombarded by a shower of high-energy neutrons, which originate from the interactions of cosmic rays with the outer layers of the atmosphere. The neutron flux changes with altitude, reaching a peak very close to the cruise altitude of airplanes, posing an even more serious threat to avionics. In addition, inevitable radioactive contaminants in the chip materials emit alpha particles, which may reach sensitive device areas and produce errors. Spacecraft and satellite electronics must operate reliably in a much harsher environment, characterized by a significant presence of ionizing radiation, in the form of protons, electrons, and heavy-ions coming from various sources. Ionizing radiation can cause either permanent or temporary damage to electronic chips, generating a plethora of effects, from flipping an SRAM memory bit from 1 to 0 or vice versa, to burning-out a power MOSFET.
M. Bagatin, G. Cellere, S. Gerardin, A. Paccagnella
Backmatter
Metadaten
Titel
Inside NAND Flash Memories
verfasst von
Rino Micheloni
Luca Crippa
Alessia Marelli
Copyright-Jahr
2010
Verlag
Springer Netherlands
Electronic ISBN
978-90-481-9431-5
Print ISBN
978-90-481-9430-8
DOI
https://doi.org/10.1007/978-90-481-9431-5

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