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2011 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

VLSI Physical Design: From Graph Partitioning to Timing Closure

verfasst von: Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

Verlag: Springer Netherlands

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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Über dieses Buch

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. VLSI Physical Design: From Graph Partitioning to Timing Closure introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
The design and optimization of integrated circuits (ICs) are essential to the production of new semiconductor chips. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to reflect improvements in semiconductor technologies and increasing design complexities. A user of this software needs a high-level understanding of the implemented algorithms. On the other hand, a developer of this software must have a strong computerscience background, including a keen understanding of how various algorithms operate and interact, and what their performance bottlenecks are.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 2. Netlist and System Partitioning
Abstract
The design complexity of modern integrated circuits has reached unprecedented scale, making full-chip layout, FPGA-based emulation and other important tasks increasingly difficult. A common strategy is to partition or divide the design into smaller portions, each of which can be processed with some degree of independence and parallelism. A divide-and-conquer strategy for chip design can be implemented by laying out each block individually and reassembling the results as geometric partitions. Historically, this strategy was used for manual partitioning, but became infeasible for large netlists. Instead, manual partitioning can be performed in the context of system-level modules by viewing them as single entities, in cases where hierarchical information is available. In contrast, automated netlist partitioning (Secs. 2.1–2.4) can handle large netlists and can redefine a physical hierarchy of an electronic system, ranging from boards to chips and from chips to blocks. Traditional netlist partitioning can be extended to multilevel partitioning (Sec. 2.5), which can be used to handle large-scale circuits and system partitioning on FPGAs (Sec. 2.6).
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 3. Chip Planning
Abstract
Chip planning deals with large modules such as caches, embedded memories, and intellectual property (IP) cores that have known areas, fixed or changeable shapes, and possibly fixed locations. When modules are not clearly specified, chip planning relies on netlist partitioning (Chap. 2) to identify such modules in large designs. Assigning shapes and locations to circuit modules during chip planning produces blocks, and enables early estimates of interconnect length, circuit delay and chip performance. Such early analysis can identify modules that need improvement. Chip planning consists of three major stages (1) floorplanning, (2) pin assignment, and (3) power planning.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 4. Global and Detailed Placement
Abstract
After partitioning the circuit into smaller modules and floorplanning the layout to determine block outlines and pin locations, placement seeks to determine the locations of standard cells or logic elements within each block while addressing optimization objectives, e.g., minimizing the total length of connections between elements. Specifically, global placement (Sec. 4.3) assigns general locations to movable objects, while detailed placement (Sec. 4.4) refines object locations to legal cell sites and enforces nonoverlapping constraints. The detailed locations enable more accurate estimates of circuit delay for the purpose of timing optimization.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 5. Global Routing
Abstract
During global routing, pins with the same electric potential are connected using wire segments. Specifically, after placement (Chap. 4), the layout area is represented as routing regions (Sec. 5.4) and all nets in the netlist are routed in a systematic manner (Sec. 5.5). To minimize total routed length, or optimize other objectives (Sec. 5.3), the route of each net should be short (Sec. 5.6). However, these routes often compete for the same set of limited resources. Such conflicts can be resolved by concurrent routing of all nets (Sec. 5.7), e.g., integer linear programming (ILP), or by sequential routing techniques, e.g., rip-up and reroute. Several algorithmic techniques enable scalability of modern global routers (Sec. 5.8).
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 6. Detailed Routing
Abstract
Recall from Chap. 5 that the layout region is represented by a coarse grid consisting of global routing cells (gcells) or more general routing regions (channels, switchboxes) during global routing. Afterward, each net undergoes detailed routing.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 7. Specialized Routing
Abstract
For signal wires in digital integrated circuits, global routing (Chap. 5) is performed first, and detailed routing next (Chap. 6). However, some types of designs, such as analog circuits and printed circuit boards (PCBs) with gridless (trackless) routing, do not warrant this distinction. Smaller, older designs with only one or two metal layers also fall into this category. When global and detailed routing are not performed separately, area routing (Secs. 7.1–7.2) directly constructs metal routes for signal connections. Unlike routing with multiple metal layers, area routing emphasizes crossing minimization. Non-Manhattan routing is discussed in Sec. 7.3, and nets that require special treatment, such as clock signals, are discussed in Secs. 7.4–7.5.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Chapter 8. Timing Closure
Abstract
The layout of an integrated circuit (IC) must not only satisfy geometric requirements, e.g., non-overlapping cells and routability, but also meet the design’s timing constraints, e.g., setup (long-path) and hold (short-path) constraints. The optimization process that meets these requirements and constraints is often called timing closure. It integrates point optimizations discussed in previous chapters, such as placement (Chap. 4) and routing (Chaps. 5–7), with specialized methods to improve circuit performance.
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Backmatter
Metadaten
Titel
VLSI Physical Design: From Graph Partitioning to Timing Closure
verfasst von
Andrew B. Kahng
Jens Lienig
Igor L. Markov
Jin Hu
Copyright-Jahr
2011
Verlag
Springer Netherlands
Electronic ISBN
978-90-481-9591-6
Print ISBN
978-90-481-9590-9
DOI
https://doi.org/10.1007/978-90-481-9591-6

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