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2014 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Protecting Chips Against Hold Time Violations Due to Variability

verfasst von: Gustavo Neuberger, Gilson Wirth, Ricardo Reis

Verlag: Springer Netherlands

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.

The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability.

To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Process Variations and Flip-Flops
Abstract
With the development of Very-Deep Sub-Micron (VDSM) technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 2. Process Variability
Overview
Abstract
Parameter variability has always been an issue in integrated circuits. However, comparing with the size of devices, it is relatively increasing with technology evolution, as the device size shrinks in a larger scale than our control over them. Also, in the past, the variations were mostly due to imperfect process control, but now intrinsic atomistic variations become more important, as devices of atomic sizes are achieved. This parameter variation causes uncertainties in circuit design, as in timing, power dissipation, and others important properties. Figure 2.1 shows the technology scaling, to exemplify how small the devices are becoming. Approaching the atomic scale is very difficult to control the process, as only one atom can make a huge difference.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 3. Flip-Flops and Hold Time Violations
Definitions
Abstract
Digital circuits necessarily include storage elements to ensure correct operation. The most common are the flip-flops (FFs). Although they are not very difficult to use, their operation must be understood and they must be characterized due to their timing metrics. They are not immune to failures, and one failure that FFs can present is the hold time violation, if they are not carefully designed. This chapter discusses FF operation and metrics, and hold time violations.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 4. Circuits Under Test
For Characterization
Abstract
The circuits can be very sensitive to process variability, but different circuits can have different sensibilities. To have representative results, the circuits that will be fabricated to be tested must be carefully chosen. First, the sensitivity of the logic circuits will be verified through simulation in 130 and 90 nm technologies, however only the results for 90 nm will be shown in this chapter. Using MC simulations, the sensitivity of inverters (representing generic combinational circuits) and FFs will be measured. Combining them, we will verify if hold time violations are a potential problem, and if they can be generated by process variations. Finally, the circuits chosen for fabrication and measurement in silicon will be shown.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 5. Measurement Circuits
For Precise Characterization
Abstract
In this chapter, it is shown all circuits that are needed to perform the measurement of the test circuits on wafer, as published in [30]. First, the delay line that will produce the artificial skew between the FF clocks is discussed. Then the ring oscillator needed to calibrate the delay line is showed. The next step is the design of a shift register to reduce the number of inputs. Finally, we put it all together and show the final layout.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 6. Experimental Results
Of Fabricated Circuits
Abstract
In this chapter, we discuss the setup of the equipments needed to perform the measurements, and results found in these measurements. First, the basic setup is shown; and then the measurement flow followed in each circuit measurement is drawn. All the measured data with the different combinations (technologies, temperature, Vdd’s) is shown in the second part of this chapter.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 7. Systematic and Random Variability
Of Measured Results
Abstract
The total variability observed in the measured data may come from different sources. They may be wafer-to-wafer, die-to-die, intra-die, and may come from systematic or random sources.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 8. Normality Tests
Of Measured Results
Abstract
To evaluate the randomness and check if the measured variability data is a normal Gaussian, mathematical normality tests were performed in the results. There are several tests that are designed to check for normality [13, 26].
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 9. Probability of Hold Time Violations
Of Short Logic Paths
Abstract
In previous chapters, the methodology to measure the value of the race immunity of a FF was presented. Although this data is important by itself, it is more meaningful when put together with the estimate of the clock skew, and the probability of hold time violations is calculated.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 10. Protecting Circuits Against Hold Time Violations
Due to Process Variability
Abstract
In this chapter, we show how to protect digital circuits against hold time violations due to process variability. First, a motivation in this issue is drawn. Then different options of how to provide the protection are presented.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 11. Padding Efficiency
Of the Proposed Padding Algorithm
Abstract
To evaluate the algorithm proposed earlier in Chap. 10, a set of experiments were performed, comparing the proposed algorithm to other methods to protect against hold time violations.c
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Chapter 12. Final Remarks
Abstract
The current IC technologies are subject to an increasingly sensitivity to process variations. These variations affect the design of digital circuit in different ways. The focus of this book is the effect of variability on hold time violations.
Gustavo Neuberger, Gilson Wirth, Ricardo Reis
Backmatter
Metadaten
Titel
Protecting Chips Against Hold Time Violations Due to Variability
verfasst von
Gustavo Neuberger
Gilson Wirth
Ricardo Reis
Copyright-Jahr
2014
Verlag
Springer Netherlands
Electronic ISBN
978-94-007-2427-3
Print ISBN
978-94-007-2426-6
DOI
https://doi.org/10.1007/978-94-007-2427-3

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