Skip to main content

2016 | Buch

Invasive Tightly Coupled Processor Arrays

insite
SUCHEN

Über dieses Buch

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
According to the International Technology Roadmap for Semiconductors(ITRS), the CMOS process technology trend in shrinking the feature sizes, as predicted by the Moore’s law [1], has led to significant improvements in the chip’s transistor density and achievable clock frequency.
Vahid Lari
Chapter 2. Invasive Tightly Coupled Processor Arrays
Abstract
In this chapter, after introducing the principles of invasive computing and a considered multi-processor system-on-a-chip (MPSoC) architecture, we dig into deeper details by introducing Tightly Coupled Processor Arrays (TCPAs), a class of coarse-grained reconfigurable processor arrays. After briefly explaining our loop mapping methodology on such architectures, we make the following contributions for realising invasive computing concepts on TCPAs: (a) development of ultra fast, distributed, and hardware-based resource invasion strategies to acquire regions of Processing Elements (PEs) of different shapes and sizes. (b) Proposing two different design variants for realising invasion strategies at the hardware level, and evaluate their timing overheads as well as hardware costs. (c) Investigation of different signalling concepts and data structure to collect information about the number and the location of invaded PEs. (d) Development of the hardware/software interfaces for integrating TCPAs into a tiled architecture, and finally, (e) evaluation of the hardware costs and timing overheads based on prototype implementations on the basis of FPGA hardware
Vahid Lari
Chapter 3. Self-adaptive Power and Energy Management for TCPAs
Abstract
In this chapter, we propose to exploit the simple yet effective idea to power processing elements of a TCPAs on at time of invasion and to shut them down again by power gating as soon as an application retreats.
Vahid Lari
Chapter 4. On-Demand Fault Tolerance on Massively Parallel Processor Arrays
Abstract
In this chapter, we present for the first time (a) a systematic and holistic method to realise on-demand fault tolerance support on Tightly Coupled Processor Arrays (TCPAs) rather than single processors. Here, we propose (b) different level of replications, i. e., no replication, Dual Modular Redundancy (DMR), and Triple Modular Redundancy (TMR), with different capabilities for error handling for TCPAs. Here, a major contribution is to (c) apply these individual replication schemes based on a our novel reliability calculus for each of the proposed replication schemes and based on environmental conditions such as monitored Soft Error Rates (SERs) on the system. The strength of our reliability analysis is the usage of application execution characteristics that we derive from the compilation process. This will guide a system to transparently adopt suitable fault tolerance techniques upon application needs.
Vahid Lari
Chapter 5. Conclusions and Future Work
Abstract
Today’s computer systems contain chips with dense and various processor designs, comprising general-purpose processors as well as non-programmable or programmable hardware accelerators, such as Coarse-Grained Reconfigurable Arrays (CGRAs).
Vahid Lari
Metadaten
Titel
Invasive Tightly Coupled Processor Arrays
verfasst von
VAHID LARI
Copyright-Jahr
2016
Verlag
Springer Singapore
Electronic ISBN
978-981-10-1058-3
Print ISBN
978-981-10-1057-6
DOI
https://doi.org/10.1007/978-981-10-1058-3

Neuer Inhalt