Abstract
This paper describes an exact algorithm for the identification of a minimal feedback vertex set in digital circuits. The proposed algorithm makes use of graph reduction and efficient graph partitioning methods based on local properties of digital circuits. It has been implemented and applied to ISCAS-89 benchmark circuits. Previously, non-optimum solutions were found. In other cases, the optimality of the solution could not be established for all circuits. By using the proposed algorithm we obtained the optimum results for all the circuits in a relatively short CPU time.
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Supported in part by the Technion fund for the promotion of research.
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Orenstein, T., Kohavi, Z. & Pomeranz, I. An optimal algorithm for cycle breaking in directed graphs. J Electron Test 7, 71–81 (1995). https://doi.org/10.1007/BF00993315
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DOI: https://doi.org/10.1007/BF00993315