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Performance analysis of heterojunction tunnel FET device with variable Temperature

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Abstract

In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source capacitance (CGS), gate-drain capacitance (CGD), cut-off frequency (fT), and gain-bandwidth product (GBP) are studied. DC, as well as AC simulations, have been performed on the proposed device. We have achieved an ON current of 0.537 mA/µm and an OFF current of 13 fA/µm, thus achieving ION/IOFF ratio as 3.72 × 1010. The values obtained for the transconductance are 0.68 milliSiemens, cut-off frequency is 446 GHz, gate-source capacitance is 0.387 femto Farads, and gate drain capacitance is 0.694 femtoFarads. The lower values of parasitic capacitances enable the device to be helpful for the low power and analog/RF applications even at high frequencies. The device has also been investigated for the temperature analysis concerning the drain current and the capacitance calculations. It was observed that the OFF currents are strongly dependent on the temperature in the drain current characteristics of the device. All the simulations have been performed on Visual TCAD (licensed version 1.9.2–3).

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Data availability

All simulation results are available in Visual TCAD laboratory of VLSI Domain under School of Electronics and Electrical Engineerng, Lovely Professional University, Punjab, India.

References

  1. D.B. Abdi, M.J. Kumar, In-built N+ pocket pnpn tunnel field-effect transistor. IEEE Electron Device Lett. 35(12), 1170–1172 (2014)

    Article  ADS  Google Scholar 

  2. P. Agarwal, G. Saraswat, M.J. Kumar, Compact surface potential model for FD SOI MOSFET considering substrate depletion region. IEEE Trans. Electron Devices 55(3), 789–795 (2008)

    Article  ADS  Google Scholar 

  3. S.K. Sinha, S. Chaudhury, Impact of oxide thickness on gate capacitance– a comprehensive analysis on MOSFET, nanowire FET and CNTFET devices. IEEE Trans. Nanotechnol. 12, 958–964 (2013)

    Article  ADS  Google Scholar 

  4. K.K. Bhuwalka, J. Schulze, I. Eisele, Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans. Electron Devices 52(5), 909–917 (2005)

    Article  ADS  Google Scholar 

  5. S. K.Sinha,and S.Chaudhury,“Simulation and analysis of quantum capacitance in single-gate MOSFET, double-gate MOSFET and CNTFET devices for nanometre regime,”IEEE International Conference CODIS, pp.157–160,2012.

  6. V. Purwar, R. Gupta, N. Kumar, H. Awasthi, V.K. Dixit, K. Singh, S. Dubey, P.K. Tiwari, Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs. Appl. Phys. A 126(9), 1–8 (2020)

    Article  Google Scholar 

  7. K. Boucart, A.M. Ionescu, Double-gate tunnel FET With High-k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)

    Article  ADS  Google Scholar 

  8. T. Bentrcia, F. Djeffal, H. Ferhati, Z. Dibi, A comparative study on scaling capabilities of Si and SiGe nanoscale double gate tunneling FETs. Springer, Silicon 12(4), 945–953 (2020)

    Article  Google Scholar 

  9. A. Chattopadhyay, A. Mallik, Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Trans. Electron Devices 58(3), 677–683 (2011)

    Article  ADS  Google Scholar 

  10. Y. Khatami, K. Banerjee, Steep subthreshold slope n-and p-type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans. Electron Devices 56(11), 2752–2761 (2009)

    Article  ADS  Google Scholar 

  11. S.K. Sinha, S. Chaudhury, Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET. Mater. Sci. Semicond. Process. 31, 431–438 (2015)

    Article  Google Scholar 

  12. W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)

    Article  ADS  Google Scholar 

  13. I. Eisele, H. Lochner, M. Schlosser, SiGe tunnel field effect transistors. ECS Trans. 16(10), 961 (2008)

    Article  Google Scholar 

  14. S. Chander, S. Baishya, Two-dimensional model of a heterojunction silicon-on insulator tunnel field effect transistor. Superlattices and Microstruct. 90, 176–183 (2016)

    Article  ADS  Google Scholar 

  15. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329 (2011)

    Article  ADS  Google Scholar 

  16. M.R. Tripathy, A.K. Singh, K. Baral, P.K. Singh, S. Jit, “III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications. Superlattices and Microstruct. 142, 106494 (2020)

    Article  Google Scholar 

  17. P.K. Singh, K. Baral, S. Kumar, M.R. Tripathy, A.K. Singh, R.K. Upadhyay, S. Chander, S. Jit, Analytical drain current model for source pocket engineered stacked oxide SiO 2/HfO 2 cylindrical gate TFETs. Silicon (2020). https://doi.org/10.1007/s12633-020-00563-6

    Article  Google Scholar 

  18. S. Anand, R. Sarin, Analog and RF performance of doping-less tunnel FETs with Si0.55Ge0.45 source. J. Comput. Electron. 15(3), 850–856 (2016)

    Article  Google Scholar 

  19. S. Chen, H. Liu, S. Wang, W. Li, X. Wang, L. Zhao, Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor. Nanoscale Res. Lett. 13(1), 321 (2018)

    Article  ADS  Google Scholar 

  20. Q. Wang, S. Wang, H. Liu, W. Li, S. Chen, Analog/RF performance of L-and U-shaped channel tunneling field-effect transistors and their application as digital inverters. Jpn. J. Appl. Phys. 56(6), 064102 (2017)

    Article  ADS  Google Scholar 

  21. A. Sarkar, C. Sarkar, RF and analogue performance investigation of DG tunnel FET. Int. J. Electron. Lett. 1(4), 210–217 (2013)

    Article  Google Scholar 

  22. P.N. Kondekar, K. Nigam, S. Pandey, D. Sharma, Electrically doped tunnel FET With bandgap engineering for analog/rf applications. IEEE Trans. Electron Devices 64(2), 412–418 (2017)

    Article  ADS  Google Scholar 

  23. P.K. Singh, K. Baral, S. Kumar, S. Chander, M.R. Tripathy, A.K. Singh, S. Jit, Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis. Appl. Phys. A 126(3), 1–11 (2020)

    Google Scholar 

  24. G. Wadhwa, B. Raj, Design, simulation and performance analysis of JLTFET biosensor for high sensitivity. IEEE Trans. Nanotechnol. 18, 567–574 (2019)

    Article  ADS  Google Scholar 

  25. H.R. Ebrahimi, H. Usefi, H. Emami, G.R. Amiri, Synthesis, characterization, and sensing performance investigation of copper cadmium ferrite nanoparticles. IEEE Trans. Magn. 54(10), 1–5 (2018)

    Article  Google Scholar 

  26. S. Nosohiyan, H.R. Ebrahimi, A.A. Nourbakhsh, G.R. Amiri, Synthesis, characterization, and sensing performance investigation of nickel ferrite nanoparticles for ammonia detection. IEEE Trans. Magn. 55(12), 1–6 (2019)

    Article  Google Scholar 

  27. G.F. Fine, L.M. Cavanagh, A. Afonja, R. Binions, Metal oxide semi-conductor gas sensors in environmental monitoring. Sensors 10(6), 5469–5502 (2010)

    Article  ADS  Google Scholar 

  28. H.R. Ebrahimi, M. Parish, G.R. Amiri, B. Bahraminejad, S. Fatahian, Synthesis, characterization and gas sensitivity investigation of Ni0.5Zn0.5Fe2O4 nanoparticles. J. Magn. Magn. Mater. 414, 55–58 (2016)

    Article  ADS  Google Scholar 

  29. M. Born, K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T. Sulima, I. Eisele, “Tunnel FET: a CMOS device for high temperature applications”, Proceedings 15th International Conference Microelectronics, pp. 124–127, 2006.

  30. K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices. 54, 1725–1733 (2007)

    Article  ADS  Google Scholar 

  31. S. Chander, S.K. Sinha, S. Kumar, P.K. Singh, K. Baral, K. Singh, S. Jit, Temperature analysis of Ge/Si heterojunction SOI-tunnel FET. Superlattices and Microstruct 110, 162–170 (2017)

    Article  ADS  Google Scholar 

  32. K. Sung Hwan, S. Agarwal, Z.A. Jacobson, P. Matheu, C. Hu, T.J.K. Liu, Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett. 31(10), 1107–1109 (2010)

    Article  ADS  Google Scholar 

  33. K.H. Kao, A.S. Verhulst, W.G. Vandenberghe, B. Soree, G. Groeseneken, K. De Meyer, Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59(2), 292–301 (2011)

    Article  ADS  Google Scholar 

  34. S. Kanungo, S. Chattopadhyay, P.S. Gupta, K. Sinha, H. Rahaman, Study and analysis of the effects of sige source and pocket-doped channel on sensing performance of dielectrically modulated tunnel FET-based biosensors. IEEE Trans. Electron Devices 63(6), 2589–2596 (2016)

    Article  ADS  Google Scholar 

  35. H.W. Kim, J.H. Kim, S.W. Kim, M.C. Sun, E. Park, B.G. Park, Tunneling field-effect transistor with Si/SiGe material for high current drivability. Jpn. J. Appl. Phys. (2014). https://doi.org/10.7567/JJAP.53.06JE12

    Article  Google Scholar 

  36. W. Li, H. Liu, S. Wang, S. Chen, Z. Yang, Design of high performance Si/SiGe heterojunction tunneling FETs with a T-shaped gate. Nanoscale Res. Lett. 12(1), 198 (2017)

    Article  ADS  Google Scholar 

  37. L. Liu, D. Mohata, S. Datta, Scaling length theory of double-gate interband tunnel field-effect transistors. IEEE Trans. Electron Devices 59(4), 902–908 (2012)

    Article  ADS  Google Scholar 

  38. G. Singh, S.I. Amin, S. Anand, R.K. Sarin, Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation. Superlattices Microstruct 92, 143–156 (2016)

    Article  ADS  Google Scholar 

  39. E.D. Kurniawan, S. Yang, V. Thirunavukkarasu, Analysis of Ge-Si heterojunction nanowire tunnel FET : Impact of tunneling window of band-to-band tunneling model. J. Electrochem. Soc. 164(11), 3354–3358 (2017)

    Article  Google Scholar 

  40. I.A. Pindoo, S.K. Sinha, S. Chander, Improvement of electrical characteristics of sige source based tunnel FET device. Silicon (2020). https://doi.org/10.1007/s12633-020-00674-0

    Article  Google Scholar 

  41. 3D device simulator, Visual TCAD, Version 1.9.2–3, Reference Manual, Cogenda Pte Ltd, Singapore, 2017.

  42. W.Y. Choi, H.K. Lee, Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Nano Convergence 3(1), 1–15 (2016)

    Article  Google Scholar 

  43. E. Kane, Zener tunneling in semiconductors. J. Phys. Chem. Solids 12(2), 181–188 (1960)

    Article  ADS  Google Scholar 

  44. S. Chander, S. Baishya, S.K. Sinha, S. Kumar, P. Singh, K. Baral, M. Tripathy, A. Singh, S. Jit, Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs. Superlattices and Microstruct 131, 30–39 (2019)

    Article  ADS  Google Scholar 

  45. S. Sant, A. Schenk, K. Moselund and H. Riel, “Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs,” 74th Annual Device Research Conference (DRC), pp. 1–2, 2016.

  46. S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation. IEEE Trans. Electron Devices 56(9), 2092–2098 (2009)

    Article  ADS  Google Scholar 

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Acknowledgements

This work is carried out in Visual TCAD (licensed version 1.9.2-3) supported by center of excellence, Lovely Professional University, Punjab, India.

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Pindoo, I.A., Sinha, S.K. & Chander, S. Performance analysis of heterojunction tunnel FET device with variable Temperature. Appl. Phys. A 127, 748 (2021). https://doi.org/10.1007/s00339-021-04891-1

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