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An integrated improved CCII topology for resistive sensor application

  • Mixed Signal Letter
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Abstract

In this paper a novel low voltage low power topology of second generation current conveyor (CCII) is presented. The internal CCII stages have been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. As an application example, the here proposed CCII, designed in standard CMOS technology (AMS 0.35 μm), has been used to design an integrated resistive sensor interface, showing the capability of compensating the non idealities of passive and active components. Preliminary and post-layout simulations show an excellent linearity for what concerns sensor sensitivity.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of L’Aquila, Monteluco di Roio, Italy

    Giuseppe Ferri, Vincenzo Stornelli & Mauro Fragnoli

Authors
  1. Giuseppe Ferri
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  2. Vincenzo Stornelli
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  3. Mauro Fragnoli
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Correspondence to Giuseppe Ferri.

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Ferri, G., Stornelli, V. & Fragnoli, M. An integrated improved CCII topology for resistive sensor application. Analog Integr Circ Sig Process 48, 247–250 (2006). https://doi.org/10.1007/s10470-006-7415-3

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  • DOI: https://doi.org/10.1007/s10470-006-7415-3

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