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A new pipelined analog-to-digital converter using current conveyors

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Abstract

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm2.

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Acknowledgment

The authors would like to thank the National Science Council and Chip Implementation Center of Taiwan for the financial and technical supporting. The work was sponsored by NSC-94-2213-E-027-049.

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Authors and Affiliations

  1. Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan, R.O.C.

    Yuh-Shyan Hwang, Jiann-Jong Chen, Sing-Yen Wu, Lu-Po Liao & Chia-Chun Tsai

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  1. Yuh-Shyan Hwang
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  2. Jiann-Jong Chen
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  3. Sing-Yen Wu
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  4. Lu-Po Liao
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  5. Chia-Chun Tsai
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Correspondence to Yuh-Shyan Hwang.

Additional information

Sing-Yen Wu received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2005. His current research interests include CMOS pipelined analog-to-digital converters and mixed-signal integrated circuit.

Lu-Po Liao received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2003. His current research interests include analog integrated circuit design and mixed-signal integrated circuit design.

Chia-Chun Tsai received the Ph.D. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, 1991. From 1989 to 2005, he served at the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan. Since 2005 he has been with the Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan, where he is a Full Professor. His current research interests include VLSI design automation and mixed-signal IC designs.

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Hwang, YS., Chen, JJ., Wu, SY. et al. A new pipelined analog-to-digital converter using current conveyors. Analog Integr Circ Sig Process 50, 213–220 (2007). https://doi.org/10.1007/s10470-007-9031-2

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  • DOI: https://doi.org/10.1007/s10470-007-9031-2

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