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Sub 1 V CMOS bandgap reference design techniques: a survey

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Abstract

This paper presents a review of constraints, limitation factors and challenges to implement sub 1 V CMOS bandgap voltage reference (BVR) circuits in today’s and future submicron technology. Moreover, we provide insight analysis of BVR circuit architectures a designer can relay upon when building CMOS voltage reference.

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Acknowledgments

The authors would like to acknowledge the financial support from the Natural Sciences and Engineering Research Council of Canada (NSERC). They also wish to thank Dalton M. Colombo, Ph.D student at Federal University of Rio Grande do Sul (Porto Alegre, Brazil), and Mary-Rose Morrison for their great contributions to this work.

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Authors and Affiliations

  1. Wireless Smart Devices Labs, Computer Science Department, Université du Québec À Montréal, President Kennedy Hall, 201 President Kennedy Avenue, PK-4630, Montreal, QC, H2X 3Y7, Canada

    Christian Jésus B. Fayomi & Hervé Facpong Achigui

  2. Departamento de Engenharia Elétrica, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil

    Gilson I. Wirth

  3. Department of Physical Electronics, Tokyo Institute of Technology, Ookayama Campus, Tokyo, Japan

    Akira Matsuzawa

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  1. Christian Jésus B. Fayomi
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  2. Gilson I. Wirth
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  3. Hervé Facpong Achigui
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  4. Akira Matsuzawa
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Correspondence to Christian Jésus B. Fayomi.

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Fayomi, C.J.B., Wirth, G.I., Achigui, H.F. et al. Sub 1 V CMOS bandgap reference design techniques: a survey. Analog Integr Circ Sig Process 62, 141–157 (2010). https://doi.org/10.1007/s10470-009-9352-4

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  • DOI: https://doi.org/10.1007/s10470-009-9352-4

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