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Statistical analysis of low-power SRAM cell structure

  • Mixed Signal Letter
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Abstract

The reduction of the channel length due to scaling increases the leakage current resulting in a major contribution to the static power dissipation. In this paper, a novel SRAM cell with eight transistors is being proposed to reduce the static hence total power dissipation. When compared to the conventional 6T SRAM and NC-SRAM cell, a significant reduction in the gate leakage current, static and total power dissipation is observed in the proposed SRAM along with higher stability. In the technique employed for the proposed SRAM cell, the operating voltage is reduced in idle mode. The technique led a reduction of 31.2 % in the total power dissipation, a reduction of 40.4 % on static power dissipation, almost without any change in the stability of the cell when compared to the conventional 6T SRAM cell topology. Cadence Virtuoso tools are used for simulation with 90-nm CMOS process technology.

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References

  1. Piguet, C. (2005). Low power electronic design. Boca Raton, FL: CRC Press.

    Google Scholar 

  2. Dhanumjaya, K., Sudha, M., Giri Prasad, M.N., & Padmaraju, K. (2012). Cell stability analysis of conventional 6T dynamic 8T SRAM cell in 45 nm technology. In International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 2, April 2012.

  3. Butzen, P. F., & Ribas, R. P. (2007). Leakage current in sub-submicrometer CMOS gates, pp. 1–28. Universidade Federal do Rio Grande do Sul.

  4. Elakkumanan, P., Thondapu, C., & Sridhar, R. (2004). A gate leakage reduction strategy for sub-70 nm memory circuit. In Proceedings of IEEE Dallas/CAS Workshop, 2004, pp. 145–148.

  5. Razavipour, G., Afzali-Kusha, A., & Pedram, M. (2009). Design and analysis of two low-power SRAM cell structures. In IEEE transactions on very large scale integration (VLSI) systems, Vol. 17, No. 10, October 2009.

  6. Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2003). Digital integrated circuits. Upper Saddle River, NJ: Prentice-Hall.

    Google Scholar 

  7. Grossar, E., et al. (2006). Read stability and write-ability analysis of SRAM cells for manometer technologies. IEEE Journal of Solid-State Circuits, 41(11), 2577–2588.

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela, 769008, India

    Govind Prasad

  2. Gitam University, Hyderabad, India

    Alekhya Anand

Authors
  1. Govind Prasad
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  2. Alekhya Anand
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Correspondence to Govind Prasad.

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Prasad, G., Anand, A. Statistical analysis of low-power SRAM cell structure. Analog Integr Circ Sig Process 82, 349–358 (2015). https://doi.org/10.1007/s10470-014-0463-1

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  • DOI: https://doi.org/10.1007/s10470-014-0463-1

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