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Delay analysis of buffer inserted sub-threshold interconnects

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Abstract

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.

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Acknowledgments

The authors sincerely acknowledge with gratitude the technical and financial support received from the Ministry of Science and Technology, Department of Science and Technology (DST), Govt. of India, through Start-up Research Grant for Young Scientists (Ref. No.: YSS/2015/001122).

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Authors and Affiliations

  1. Electronics and Communication Engineering Department, National Institute of Technology Hamirpur, Hamirpur, HP, 177 005, India

    Rohit Dhiman & Rajeevan Chandel

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  1. Rohit Dhiman
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  2. Rajeevan Chandel
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Correspondence to Rohit Dhiman.

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Dhiman, R., Chandel, R. Delay analysis of buffer inserted sub-threshold interconnects. Analog Integr Circ Sig Process 90, 435–445 (2017). https://doi.org/10.1007/s10470-016-0860-8

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