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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 4/2016

04.10.2016

Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs

verfasst von: Rechem Djamil, Khial Aicha, Azizi Cherifa, Fayçal Djeffal

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2016

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Abstract

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.
Vorheriger Artikel Asymmetric junctionless nanowire TFET with built-in source pocket emphasizing on energy band modification
Nächster Artikel A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

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Metadaten
Titel
Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs
verfasst von
Rechem Djamil
Khial Aicha
Azizi Cherifa
Fayçal Djeffal
Publikationsdatum
04.10.2016
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 4/2016
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0901-7

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