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FPGA Implementation of Heart Rate Monitoring System

  • Patient Facing Systems
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Abstract

This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84 %, the sensitivity of 99.94 % and the positive predictive value of 99.89 %. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

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Authors and Affiliations

  1. Department of Electrical Engineering, NIT Rourkela, Odisha, India

    D. Panigrahy, M. Rakshit & P. K. Sahu

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  1. D. Panigrahy
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  2. M. Rakshit
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  3. P. K. Sahu
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Correspondence to D. Panigrahy.

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Panigrahy, D., Rakshit, M. & Sahu, P.K. FPGA Implementation of Heart Rate Monitoring System. J Med Syst 40, 49 (2016). https://doi.org/10.1007/s10916-015-0410-4

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