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Architecture for video coding on a processor with an ARM and DSP cores

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Abstract

This paper aims to describe architecture for video coding on a processor with an ARM and DSP cores. The proposed platform has been designed for MPEG-4 Visual Simple Profile. The obtained results are optimized if compared with these of single-core. The dual-core processors, composed of RISC and DSP, are widely used as the based-band processors of cell phones. The RISC suits for IO control, while DSP is useful for computation. The operational efficiency of the integration of RISC and DSP is outstanding. Video compression requires a great deal of computation, so we take both the feature of coding algorithm and the hardware platform into consideration. We analyze features of key components in video codec and propose the framework, which adopts DMA to shorten the time needed. It is the result of the communication between the dual-cores. The experimental results indicate that during the inter-frame processing, dual-core with DMA can cut down the processing time by 1/4 more than that of single-use of ARM or DSP. Moreover, it can save 3/4 of the time for encode/decode processing in inter-frame. Especially, in respect of motion estimation, the performance rating can be improved by 4 times.

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References

  1. Chaoui J, Cyr K, de Gregorio S, Giacalone J-P, Webb J, Masse Y (2001) Open multimedia application platform: enable multimedia applications in third generation wireless terminals through a combined RISC/DSP architecture. Proc ICASSP 2001:1009–1012

    Google Scholar 

  2. Choi B-D, Choi K-S, Ko S-J (2003) Senior Member, IEEE, and Aldo W. Morales, Senior Member, IEEE, Efficient real-time implementation of MPEG-4 audiovisual decoder using DSP and RISC chips. IEEE

  3. Hatabu A, Miyazakl T, Kuroda I (2002) QVGA/CIF resolution MPEG-4 video codec based on a low-power and general-purpose DSP, IEEE

  4. Lee KH, Lee K-S, Huang T-H, Park Y-C, Youn DH (2001) An architecture and implementation of MPEG audio layerIII decoder using dual-core DSP. IEEE Transaction on Consuner Electronics 47(4)

  5. Lehtoranta O, Hamalainen T, Saarinen J (2000) Real-time H.263 encoding of QCIF-images on TMS320C6201 fixed point DSP, ISCAS 2000- IEEE International Symposium on Circuits and Systems, May 6 28–31, Geneva, Swizerland

  6. Li P, Lu Y, Wei H, Li S (2006) Realization of embedded multimedia system based on dual-core Processor OMAP5910, IMACS Multiconference on “ Computational Engineering in Systems Applicaions”(CESA), October 4–6, 2006, Beijing, China

  7. Rader S, etc., “Mobile Extreme Convergence: A Streamlined Architecture to Deliver Mass-market Converged Mobile Devices,” Freescale white paper

  8. Shen T-F (2008) Design and analysis of a dynamic task partitioning approach for video decoding on heterogeneous dual-core platforms,” master thesis, NCTU, June 2008

  9. Stolberg H-J, Berekovic M, Friebe L, Moch S, Flügel S, Mao X, Kulaczewski MB, Klubmann H, Pirsch P (2003) HiBRID-SoC: A MuLTI-Core System on Chip Architecture for Multimedia Signal Processing Applications, Proceedings of Design, Automation and Test in Europe Conference and Exhibition(DATE’03), IEEE

  10. Texas Instruments, Inc., TMS320C55X DSP Programmer’s Guide

  11. Texas Instruments, Inc., TMS320C55X Image/Video Processing Library Programmer’s Reference

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Authors and Affiliations

  1. National Taiwan University of Science and Technology, Taipei, Taiwan, Republic of China

    Yung-Sung Huang & Bin-Chang Chieu

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  1. Yung-Sung Huang
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  2. Bin-Chang Chieu
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Correspondence to Yung-Sung Huang.

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Huang, YS., Chieu, BC. Architecture for video coding on a processor with an ARM and DSP cores. Multimed Tools Appl 54, 527–543 (2011). https://doi.org/10.1007/s11042-010-0550-y

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  • DOI: https://doi.org/10.1007/s11042-010-0550-y

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