Skip to main content
Erschienen in: The Journal of Supercomputing 2/2018

03.11.2017

A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links

verfasst von: Zeynab Mohseni, Midia Reshadi

Erschienen in: The Journal of Supercomputing | Ausgabe 2/2018

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

In recent years, the idea of wireless three-dimensional network-on-chips (3D NoCs) was promoted in order to design many-core chips with greater performance and lower energy consumption. This technology is the combination of different dies that are stacked on each other. Therefore, it is necessary to propose a suitable routing mechanism for irregular wireless 3D NoCs that can support the agnostic topologies. In this paper, we propose a deadlock-free routing algorithm for wireless 3D NoCs, called Floyd-base Inter-chip Traffic distribution (FIT), which is based on Floyd routing algorithm. In FIT algorithm, the number of hops is reduced compared to the already established deterministic algorithms; moreover, the traffic distribution is improved. Evaluation results show that our proposed routing algorithm significantly improves the performance and throughput by reducing the energy consumption, the average hop count and the communication latency.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Micheli GD, Benini L (2006) Network on chips: technology and tools. In: Systems on Silicon Micheli GD, Benini L (2006) Network on chips: technology and tools. In: Systems on Silicon
2.
Zurück zum Zitat Chan J, Parameswaran S (2004) NoCGEN: a template based reuse methodology for networks on chip architecture. In: Proceedings of the 17th International Conference on VLSI Design, Jan 2004, pp 717–720 Chan J, Parameswaran S (2004) NoCGEN: a template based reuse methodology for networks on chip architecture. In: Proceedings of the 17th International Conference on VLSI Design, Jan 2004, pp 717–720
3.
Zurück zum Zitat Kumar S, Jantsch A, Soininen JP, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2002) A network on chip architecture and design methodology. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Apr 2002, pp 105–112 Kumar S, Jantsch A, Soininen JP, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2002) A network on chip architecture and design methodology. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Apr 2002, pp 105–112
4.
Zurück zum Zitat Feero BS, Pande PP (2009) Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans Comput 58(1):32–45MathSciNetCrossRefMATH Feero BS, Pande PP (2009) Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans Comput 58(1):32–45MathSciNetCrossRefMATH
5.
Zurück zum Zitat Hasan Furhad Md, Kim JM (2014) A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures. J Supercomput 69(2):766–792CrossRef Hasan Furhad Md, Kim JM (2014) A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures. J Supercomput 69(2):766–792CrossRef
6.
Zurück zum Zitat Touzene A, Day Kh (2015) All-to-all broadcasting in torus network on chip. J Supercomput 71(7):2585–2596CrossRef Touzene A, Day Kh (2015) All-to-all broadcasting in torus network on chip. J Supercomput 71(7):2585–2596CrossRef
7.
Zurück zum Zitat Matsutani H, Koibuchi M, Fujiwara I, Kagami T (2014) Low-latency wireless 3D NoCs via randomized shortcut chips. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6 Matsutani H, Koibuchi M, Fujiwara I, Kagami T (2014) Low-latency wireless 3D NoCs via randomized shortcut chips. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6
8.
Zurück zum Zitat Burns J, McIlrath L, Keast C, Lewis C, Loomis A, Warner K, Wyatt P (2001) Three-dimensional integrated circuits for low-power high- bandwidth systems on a chip. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’01), pp 268–269 Burns J, McIlrath L, Keast C, Lewis C, Loomis A, Warner K, Wyatt P (2001) Three-dimensional integrated circuits for low-power high- bandwidth systems on a chip. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’01), pp 268–269
9.
Zurück zum Zitat Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule AM, Steer M, Franzon PD (2005) Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des Test Comput 22(6):498–510CrossRef Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule AM, Steer M, Franzon PD (2005) Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des Test Comput 22(6):498–510CrossRef
10.
Zurück zum Zitat Feero BS, Pande PP (2011) Three-dimensional networks-on-chip: performance evaluation. In: Integrated Circuits and Systems. Springer, pp 115–145 Feero BS, Pande PP (2011) Three-dimensional networks-on-chip: performance evaluation. In: Integrated Circuits and Systems. Springer, pp 115–145
11.
Zurück zum Zitat Chen KC, Lin SY, Hung HS, Wu AA (2013) Topology-aware adaptive routing for nonstationary irregular mesh in throttled 3D NoC systems. IEEE Trans Parallel Distrib Syst 24(10):2109–2120CrossRef Chen KC, Lin SY, Hung HS, Wu AA (2013) Topology-aware adaptive routing for nonstationary irregular mesh in throttled 3D NoC systems. IEEE Trans Parallel Distrib Syst 24(10):2109–2120CrossRef
12.
Zurück zum Zitat Dally WJ, Towles B (2004) Principles and practices of interconnection networks. Morgan Kaufmann publishers is an imprint of Elsevier Dally WJ, Towles B (2004) Principles and practices of interconnection networks. Morgan Kaufmann publishers is an imprint of Elsevier
13.
Zurück zum Zitat Topol AW, La Tulipe DC, Shi L, Frank DJ (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4.5):491–506CrossRef Topol AW, La Tulipe DC, Shi L, Frank DJ (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4.5):491–506CrossRef
14.
Zurück zum Zitat Ben Ahmed A, Ben Abdallah A (2013) Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 66(3):1507–1532CrossRef Ben Ahmed A, Ben Abdallah A (2013) Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 66(3):1507–1532CrossRef
15.
Zurück zum Zitat Matsutani H, Bogdan P, Marculescu R, Take Y, Sasaki D, Zhang H, Koibuchi M, Kuroda T, Amano H (2013) A case wireless 3D NoCs for CMPs. In: Design Automation Conference (ASP-DAC), 18th Asia and South Pacific, pp 23–28 Matsutani H, Bogdan P, Marculescu R, Take Y, Sasaki D, Zhang H, Koibuchi M, Kuroda T, Amano H (2013) A case wireless 3D NoCs for CMPs. In: Design Automation Conference (ASP-DAC), 18th Asia and South Pacific, pp 23–28
16.
Zurück zum Zitat Take Y, Matsutani H, Sasaki D, Koibuchi M, Kuroda T, Amano H (2014) 3D NoC with inductive-coupling links for building-block SiPs. IEEE Trans Comput 63(3):748–763MathSciNetCrossRefMATH Take Y, Matsutani H, Sasaki D, Koibuchi M, Kuroda T, Amano H (2014) 3D NoC with inductive-coupling links for building-block SiPs. IEEE Trans Comput 63(3):748–763MathSciNetCrossRefMATH
17.
Zurück zum Zitat Agyeman MO, Ahmadinia A, Shahrabi A (2013) Efficient routing techniques in heterogeneous 3D networks-on-chip. Parallel Comput 39(9):389–407CrossRef Agyeman MO, Ahmadinia A, Shahrabi A (2013) Efficient routing techniques in heterogeneous 3D networks-on-chip. Parallel Comput 39(9):389–407CrossRef
18.
Zurück zum Zitat Wang X, Yang M, Jiang Y, Palesi M, Liu P, Mak T, Bagherzade N (2013) Efficient multicast schemes for 3-D networks-on-chip. J Syst Archit 59(9):693–708CrossRef Wang X, Yang M, Jiang Y, Palesi M, Liu P, Mak T, Bagherzade N (2013) Efficient multicast schemes for 3-D networks-on-chip. J Syst Archit 59(9):693–708CrossRef
19.
Zurück zum Zitat Wu R, Wang Y, Zhao D (2010) A low-cost deadlock-free design of minimal-table rerouted XY-routing for irregular wireless NoCs. In: 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2010, pp 199–206 Wu R, Wang Y, Zhao D (2010) A low-cost deadlock-free design of minimal-table rerouted XY-routing for irregular wireless NoCs. In: 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2010, pp 199–206
20.
Zurück zum Zitat Ahmed AB, Abdallah AB (2014) Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architectures. J Parallel Distrib Comput 74(4):2229–2240CrossRef Ahmed AB, Abdallah AB (2014) Graceful deadlock-free fault-tolerant routing algorithm for 3D network-on-chip architectures. J Parallel Distrib Comput 74(4):2229–2240CrossRef
21.
Zurück zum Zitat Chao CH, Jheng KY, Wang HY, Wu JC, Wu AY (2010) Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems. In: 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS) May 2010, pp 223–230 Chao CH, Jheng KY, Wang HY, Wu JC, Wu AY (2010) Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems. In: 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS) May 2010, pp 223–230
22.
Zurück zum Zitat Shamim MS, Ganguly A, Munuswamy C, Venkatarman J, Hernandez J, Kandlikar S (2015) Co-design of 3D wireless network-on-chip architectures with microchannel-based cooling. In: Sixth International Green Computing Conference and Sustainable Computing Conference (IGSC), Las Vegas, Nov 2015, pp 1–6 Shamim MS, Ganguly A, Munuswamy C, Venkatarman J, Hernandez J, Kandlikar S (2015) Co-design of 3D wireless network-on-chip architectures with microchannel-based cooling. In: Sixth International Green Computing Conference and Sustainable Computing Conference (IGSC), Las Vegas, Nov 2015, pp 1–6
23.
Zurück zum Zitat More A, Taskin B (2010) Wireless interconnects for inter-tier communication on 3D ICs. In: Microwave Conference (EuMC), European, Paris, pp 105–108 More A, Taskin B (2010) Wireless interconnects for inter-tier communication on 3D ICs. In: Microwave Conference (EuMC), European, Paris, pp 105–108
24.
Zurück zum Zitat Kiani V, Reshadi M (2017) Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links. J Supercomput 73(5):2187–2213CrossRef Kiani V, Reshadi M (2017) Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links. J Supercomput 73(5):2187–2213CrossRef
25.
Zurück zum Zitat Miura N, Ishikuro H, Sakurai T, Kuroda T (2007) A 0.14pJ/b inductive- coupling inter-chip data transceiver with digitally-controlled precise pulse shaping. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’07), pp 358–359 Miura N, Ishikuro H, Sakurai T, Kuroda T (2007) A 0.14pJ/b inductive- coupling inter-chip data transceiver with digitally-controlled precise pulse shaping. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’07), pp 358–359
26.
Zurück zum Zitat Ouyang J, Xie J, Poremba M, Xie Y (2010) Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. In: IEEE/ACM International Conference on Computer-Aided Design(ICCAD), Nov 2010, pp 477–482 Ouyang J, Xie J, Poremba M, Xie Y (2010) Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. In: IEEE/ACM International Conference on Computer-Aided Design(ICCAD), Nov 2010, pp 477–482
27.
Zurück zum Zitat Lee J, Zhu M, Choi K, Ho Ahn J, Sharma R (2011) 3D network-on-chip with wireless links through inductive coupling. In: SoC Design Conference(ISOCC). IEEE, pp 353–356 Lee J, Zhu M, Choi K, Ho Ahn J, Sharma R (2011) 3D network-on-chip with wireless links through inductive coupling. In: SoC Design Conference(ISOCC). IEEE, pp 353–356
28.
Zurück zum Zitat Zhang Z, Yin S, Liu L, Wei S (2013) An inductive-coupling interconnected application-specific 3D NoC design. In: IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp 550–553 Zhang Z, Yin S, Liu L, Wei S (2013) An inductive-coupling interconnected application-specific 3D NoC design. In: IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp 550–553
29.
Zurück zum Zitat Concer N, Bononi L, Soulie M, Locatelli R, Carloni LP (2010) The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(6):869–882CrossRef Concer N, Bononi L, Soulie M, Locatelli R, Carloni LP (2010) The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(6):869–882CrossRef
30.
Zurück zum Zitat Salminen E, Kulmala A, Hamalainen TD (2008) Survey of network-on-chip proposals. In: Tampere University of Echnology, P.O.Box 553, FIN-33101 Tempere, Finland Salminen E, Kulmala A, Hamalainen TD (2008) Survey of network-on-chip proposals. In: Tampere University of Echnology, P.O.Box 553, FIN-33101 Tempere, Finland
31.
Zurück zum Zitat Duato J, Yalamanchili S, Ni L (2004) Interconnection networks: an engineering approach. In: Morgan Kaufmann publishers an imprint of Elsevier science Duato J, Yalamanchili S, Ni L (2004) Interconnection networks: an engineering approach. In: Morgan Kaufmann publishers an imprint of Elsevier science
32.
Zurück zum Zitat de Mello AV, Ost LC, Moraes FG, Calazans NLV (2004) Evaluation of routing algorithms on mesh based NoCs. In: PUCRS de Mello AV, Ost LC, Moraes FG, Calazans NLV (2004) Evaluation of routing algorithms on mesh based NoCs. In: PUCRS
33.
Zurück zum Zitat Chiu GM (2000) The odd-even turn model for adaptive routing. In: IEEE Transactions on Parallel and Distributed Systems, pp 729–738 Chiu GM (2000) The odd-even turn model for adaptive routing. In: IEEE Transactions on Parallel and Distributed Systems, pp 729–738
34.
Zurück zum Zitat Wettin P, Murray J, Kim R, Yu X, Pande PP, Heo D (2014) Performance evaluation of wireless NoCs in presence of irregular network routing strategies. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6 Wettin P, Murray J, Kim R, Yu X, Pande PP, Heo D (2014) Performance evaluation of wireless NoCs in presence of irregular network routing strategies. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 1–6
35.
Zurück zum Zitat Koibuchi M, Funahashi A, Jouraku A, Amano H (2001) L-turn routing: an adaptive routing in irregular networks. In: International Conference on Parallel Processing, Sep 2001, pp 383–392 Koibuchi M, Funahashi A, Jouraku A, Amano H (2001) L-turn routing: an adaptive routing in irregular networks. In: International Conference on Parallel Processing, Sep 2001, pp 383–392
36.
Zurück zum Zitat Sun YM, Yang CH, Chung YC, Huang TY (2004) An efficient deadlock-free tree-based routing algorithm for irregular wormhole-routed networks based on the turn model. In: International Conference on Parallel Processing, ICPP 2004, Aug 2004, vol 1, pp 343–352 Sun YM, Yang CH, Chung YC, Huang TY (2004) An efficient deadlock-free tree-based routing algorithm for irregular wormhole-routed networks based on the turn model. In: International Conference on Parallel Processing, ICPP 2004, Aug 2004, vol 1, pp 343–352
37.
Zurück zum Zitat Wu J, Sheng L (1999) Deadlock-free routing in irregular networks using prefix routing. In: 12th International Conference on ISCA, Apr 1999 Wu J, Sheng L (1999) Deadlock-free routing in irregular networks using prefix routing. In: 12th International Conference on ISCA, Apr 1999
38.
Zurück zum Zitat Lysne O, Skeie T, Reinemo SA, Theiss I (2006) Layered routing in irregular networks. IEEE Trans Parallel Distrib Syst 17(1):51–65CrossRef Lysne O, Skeie T, Reinemo SA, Theiss I (2006) Layered routing in irregular networks. IEEE Trans Parallel Distrib Syst 17(1):51–65CrossRef
39.
Zurück zum Zitat Skeie T, Lysne O, Theiss I (2001) Layered shortest path (LASH) routing in irregular system area networks. In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS 2002, Abstracts and CD-ROM Skeie T, Lysne O, Theiss I (2001) Layered shortest path (LASH) routing in irregular system area networks. In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS 2002, Abstracts and CD-ROM
40.
Zurück zum Zitat Solheim AG, Lysne O, Skeie T, Sodring T (2006) Routing for the asi fabric manager. IEEE Commun Mag 44(7):39–44CrossRef Solheim AG, Lysne O, Skeie T, Sodring T (2006) Routing for the asi fabric manager. IEEE Commun Mag 44(7):39–44CrossRef
41.
Zurück zum Zitat Moraveji R, Sarbazi-Azad H (2008) Direction-based routing methodology for irregular NoCs. In: International SoC Design Conference, ISOCC ’08 1:285–287 Moraveji R, Sarbazi-Azad H (2008) Direction-based routing methodology for irregular NoCs. In: International SoC Design Conference, ISOCC ’08 1:285–287
42.
Zurück zum Zitat Moraveji R, Sarbazi-Azad H, Zomaya AY (2010) A general methodology for direction-based irregular routing algorithms. J Parallel Distrib Comput 70(4):363–370CrossRefMATH Moraveji R, Sarbazi-Azad H, Zomaya AY (2010) A general methodology for direction-based irregular routing algorithms. J Parallel Distrib Comput 70(4):363–370CrossRefMATH
43.
Zurück zum Zitat Chou CL, Marculescu R (2008) Contention-aware application mapping for network-on-chip communication architectures. In: IEEE International Conference on Computer Design, ICCD 2008, Oct 2008, pp 164–169 Chou CL, Marculescu R (2008) Contention-aware application mapping for network-on-chip communication architectures. In: IEEE International Conference on Computer Design, ICCD 2008, Oct 2008, pp 164–169
44.
Zurück zum Zitat Lin S-Y, Huang C-H, Chao C-H, Huang K-H, Wu A-Y (2008) Traffic-balanced routing algorithm for irregular mesh-based on-chip networks. IEEE Trans Comput 57(9):1156–1168MathSciNetCrossRef Lin S-Y, Huang C-H, Chao C-H, Huang K-H, Wu A-Y (2008) Traffic-balanced routing algorithm for irregular mesh-based on-chip networks. IEEE Trans Comput 57(9):1156–1168MathSciNetCrossRef
45.
Zurück zum Zitat Palesi M, Longo G, Signorino S, Holsmark R, Kumar S, Catania V (2008) Design of bandwidth aware and congestion avoiding efficient routing algorithms for networks-on-chip platforms. In: 2nd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008, Apr 2008, pp 97–106 Palesi M, Longo G, Signorino S, Holsmark R, Kumar S, Catania V (2008) Design of bandwidth aware and congestion avoiding efficient routing algorithms for networks-on-chip platforms. In: 2nd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008, Apr 2008, pp 97–106
46.
Zurück zum Zitat Chi HC, Tang CT (1997) A deadlock-free routing scheme for interconnection networks with irregular topologies. In: Proceedings of the International Conference on Parallel and Distributed Systems, Dec 1997, pp 88–95 Chi HC, Tang CT (1997) A deadlock-free routing scheme for interconnection networks with irregular topologies. In: Proceedings of the International Conference on Parallel and Distributed Systems, Dec 1997, pp 88–95
47.
Zurück zum Zitat Ebrahimi M, Daneshtalab M (2017) EbDa: a new theory on design and verification of deadlock-free interconnection networks. In: Proceedings of ISCA ’17, pp 1–13 Ebrahimi M, Daneshtalab M (2017) EbDa: a new theory on design and verification of deadlock-free interconnection networks. In: Proceedings of ISCA ’17, pp 1–13
48.
Zurück zum Zitat Lu Z (2007) Design and analysis of on-chip communication for network-on-chip platforms, from Royal Institute of Technology (KTH), Sweden Lu Z (2007) Design and analysis of on-chip communication for network-on-chip platforms, from Royal Institute of Technology (KTH), Sweden
49.
Zurück zum Zitat Duato J (2002) Interconnection Networks. Morgan Kaufmann publishers is an imprint of Elsevier Duato J (2002) Interconnection Networks. Morgan Kaufmann publishers is an imprint of Elsevier
51.
Zurück zum Zitat Jerger NE, Peh LS (2009) On-chip networks. In: Synthesis Lectures on Computer Architecture Jerger NE, Peh LS (2009) On-chip networks. In: Synthesis Lectures on Computer Architecture
52.
Zurück zum Zitat Flich J, Rodrigo S, Duato J (2008) An efficient implementation of distributed routing algorithms for NoCs. In: 2nd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008, Apr 2008, pp 87–96 Flich J, Rodrigo S, Duato J (2008) An efficient implementation of distributed routing algorithms for NoCs. In: 2nd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2008, Apr 2008, pp 87–96
53.
Zurück zum Zitat Choudhary N, Samota CM (2013) A survey of logic based distributed routing for on-chip interconnection networks. IJSCE 3(2):233–237 Choudhary N, Samota CM (2013) A survey of logic based distributed routing for on-chip interconnection networks. IJSCE 3(2):233–237
54.
Zurück zum Zitat Chen KC, Kuo CC, Hung HS, Wu A-YA (2013) Traffic- and thermal-aware adaptive beltway routing for three dimensional network-on-chip systems. In: IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp 1660–1663 Chen KC, Kuo CC, Hung HS, Wu A-YA (2013) Traffic- and thermal-aware adaptive beltway routing for three dimensional network-on-chip systems. In: IEEE International Symposium on Circuits and Systems (ISCAS), May 2013, pp 1660–1663
Metadaten
Titel
A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links
verfasst von
Zeynab Mohseni
Midia Reshadi
Publikationsdatum
03.11.2017
Verlag
Springer US
Erschienen in
The Journal of Supercomputing / Ausgabe 2/2018
Print ISSN: 0920-8542
Elektronische ISSN: 1573-0484
DOI
https://doi.org/10.1007/s11227-017-2173-9

Weitere Artikel der Ausgabe 2/2018

The Journal of Supercomputing 2/2018 Zur Ausgabe