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Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

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Abstract

Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.

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Authors and Affiliations

  1. IMEC vzw, Kapeldreef 75, Heverlee, 3001, Belgium

    B. Mei, B. De Sutter, T. Vander Aa, M. Wouters & S. Dupont

  2. Freescale Semiconductor, 134 Av. du General Eisenhower, Toulouse, 31023, France

    A. Kanstein

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  1. B. Mei
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  2. B. De Sutter
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  3. T. Vander Aa
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  4. M. Wouters
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  5. A. Kanstein
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  6. S. Dupont
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Correspondence to B. Mei.

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Mei, B., De Sutter, B., Vander Aa, T. et al. Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. J Sign Process Syst Sign Image 51, 225–243 (2008). https://doi.org/10.1007/s11265-007-0152-8

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  • DOI: https://doi.org/10.1007/s11265-007-0152-8

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