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Compilers for Low Power with Design Patterns on Embedded Multicore Systems

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Abstract

Minimization of power dissipation can be considered at algorithmic, compiler, architectural, logic, and circuit level. Recent research trends for multicore programming models have come to the direction that parallel design patterns can be a solution to develop multicore applications. As parallel design patterns are with regularity, we view this as a great opportunity to exploit power optimizations in the software layer. In this paper, we investigate compilers for low power with parallel design patterns on embedded multicore systems. We evaluate four major parallel design patterns, Pipe and Filter, MapReduce with Iterator, Puppeteer, and Bulk Synchronous Parallel (BSP) Model. Our work attempts to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs. The proposed optimization schemes are rate-based optimization for Pipe and Filter pattern , early-exit power optimization for MapReduce with Iterator pattern, power aware mapping algorithm for Puppeteer pattern, and multi-phases power gating scheme for BSP pattern. In our experiments, real world multicore applications are evaluated on a multicore power simulator. Significant power reductions are observed from the experimental results. Therefore, we present a direction for power optimizations that one can further identify additional key design patterns for embedded multicore systems to explore power optimization opportunities via compilers.

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Acknowledgments

This work is supported in part by Ministry of Economic Affairs under grant no. 101-EC-17-A-02-S1-202 and National Science Council under grant no.102-2219-E-007-001 and 102-2220-E-007-001 in Taiwan. The authors also greatly appreciate Prof. Shang-Hong Lai and his student Yu-Chun Chen and Te-Feng Su of National Tsing Hua University, Taiwan for providing the vehicle detection application as a test case in our experiments.

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  1. Department of Computer Science, National Tsing Hua University, Hsinchu City, Taiwan

    Cheng-Yen Lin, Chi-Bang Kuan, Wen-Li Shih & Jenq Kuen Lee

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  1. Cheng-Yen Lin
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Correspondence to Jenq Kuen Lee.

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Lin, CY., Kuan, CB., Shih, WL. et al. Compilers for Low Power with Design Patterns on Embedded Multicore Systems. J Sign Process Syst 80, 277–293 (2015). https://doi.org/10.1007/s11265-014-0917-9

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  • DOI: https://doi.org/10.1007/s11265-014-0917-9

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