Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits’ delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (V_th), mobility of carriers (μ₀), oxide thickness (t_ox) and doping concentration (n_sd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 × 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (1×, 2×, 3× and 4× output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.