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State-of-the-art flash memory devices and post-flash emerging memories

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Abstract

Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined.

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References

  1. Lu C Y, Kuan H. Nonvolatile semiconductor memory revolutionizing information storage. IEEE Nanotech Mag, 2009, 3: 4–9

    Article  Google Scholar 

  2. Servalli G, Brazzelli D, Camerlenghi E, et al. A 65 nm NOR flash technology with 0.042 μm2 cell size for high performance multilevel application. In: International Electron Device Meeting (IEDM), session 35-1, 2005. 869–872

  3. Fastow R, Banerjee R, Bjeletich P, et al. A 45 nm NOR flash technology with self-aligned contacts and 0.024 μm2 cell size for multi-level applications. In: VLSI Technology, System and Applications (VLSI-TSA), 2008. 81–82

  4. Kuchibhatla R. IMFT 25-nm MLC NAND: technology scaling barrier broken. In: EE Times News and Analysis, March 22, 2010

  5. Darling P. Intel, Micron First to Sample 3-Bit-Per-Cell NAND Flash Memory on Industry-Leading 25-Nanometer Silicon Processing Technology. Micron Technology Inc. Press Release, August 17, 2010

  6. Lue H T, Hsu T H, Lai S C, et al. Scaling evaluation of BE-SONOS NAND flash beyond 20 nm. In: VLSI Symposia on Technology, session 12-1, 2008. 116–117

  7. Lee C H, Choi K I, Cho M K, et al. A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories. In: International Electron Device Meeting (IEDM), session 26-5, 2003. 613–616

  8. Lai S C, Lue H T, Liao C W, et al. An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3. In: NVSMW-ICMTD, 2008. 101–102

  9. Lue H T, Wang S Y, Lai E K, et al. BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability. In: International Electron Device Meeting (IEDM), session 22-3, 2005. 555–558

  10. Lue H T, Wang S Y, Hsiao Y H, et al. Reliability model of bandgap engineered SONOS (BE-SONOS). In: International Electron Device Meeting (IEDM), session 18-5, 2006. 495–498

  11. Lai S C, Lue H T, Yang M J, et al. MA BE-SONOS: A bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation. In: IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW), 2007. 88–89

  12. Lue H T, Lai S C, Hsu T H, et al. Modeling of barrier engineered charge-trapping NAND flash (BE CTNF) devices. IEEE Trans Device Mater Reliab (TDMR), 2010, 10: 222–232

    Article  Google Scholar 

  13. Lue H T, Pan J F, Wang S Y, et al. Chip-level reliability study of barrier engineered (BE) floating gate (FG) flash memory devices. In: International Reliability Physics Symposium (IRPS), session 5D-2, 2010. 627–633

  14. Hsieh C C, Lue H T, Chang K P, et al. A novel BE-SONOS NAND flash using non-cut trapping layer with superb reliability. In: International Electron Device Meeting (IEDM), session 5, 2010. to be published

  15. Lue H T, Hsu T H, Lai S C, et al. Study of electron and hole injection statistics of BE-SONOS NAND flash. In: International Memory Workshop (IMW), 2010. 92–95

  16. Compagnoni C M, Spinelli A S, Gusmeroli R, et al. Ultimate accuracy for the NAND Flash program algorithm due to the electron injection statistics. In: IEEE T-ED, 2008. 2695–2702

  17. Hsiao Y H, Lue H T, Hsieh K Y, et al. A study of stored charge interference and fringing field effects in sub-30 nm charge-trapping NAND flash. In: International Memory Workshop (IMW), 2009. 34–35

  18. Prall K, Parat K. 25 nm 64 Gb MLC NAND technology and scaling challenges. In: International Electron Device Meeting (IEDM), session 5-5, 2010. 98–101

  19. Lai E K, Lue H T, Hsiao Y H, et al. A multi-layer stackable thin-film transistor (TFT) NAND-type flash memory. In: International Electron Device Meeting (IEDM), session 2-4, 2006. 41–44

  20. Jung S M, Jang J, Cho W, et al. Three dimensionally stacked NAND flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node. In: International Electron Device Meeting (IEDM), 2006. 37–40

  21. Tanaka H, Kido M, Yahashi K, et al. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: VLSI Symposia on Technology, 2007. 14–15

  22. Katsumata R, Kito M, Fukuzumi Y, et al. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices. In: VLSI Symposia on Technology, 2009. 136–137

  23. Jang J, Kim H S, Cho W, et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory. In: VLSI Symposia on Technology, 2009. 192–193

  24. Kim J, Hong A J, Kim S M, et al. Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive). In: VLSI Symposia on Technology, 2009. 186–187

  25. Kim W, Choi S, Sung J, et al. Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage. In: VLSI Symposia on Technology, 2009. 188–189

  26. Lue H T, Hsu T H, Hsiao Y H, et al. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device. In: VLSI Symposia on Technology, 2010. 131–132

  27. Hsu T H, Lue H T, Hsieh C C, et al. Study of sub-30 nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application. In: International Electron Device Meeting (IEDM), session 27-4, 2009. 629–632

  28. Hubert A, Nowak E, Tachi K, et al. A stacked SONOS technology, up to 4 levels and 6 nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration. In: International Electron Device Meeting (IEDM), 2009. 637–640

  29. Chen Y C, Rettner C T, Raoux S, et al. Ultra-thin phase-change bridge memory device using GeSb. In: International Electron Device Meeting (IEDM), session 30-3, 2006. 777–780

  30. Oh J H, Park J H, Lim Y S, et al. Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. In: International Electron Device Meeting (IEDM), session 2-6, 2006. 49–52

  31. Servalli G. A 45 nm generation phase change memory technology. In: International Electron Device Meeting (IEDM), session 5-7, 2009. 113–116

  32. Kittel C. Introduction to Solid State Physics. 7th ed. New York: Wiley, 1996. 393–398

    Google Scholar 

  33. Ishiwara H. Current status and prospects of ferroelectric memories. In: International Electron Device Meeting (IEDM), session 33-1, 2001. 725–728

  34. Takashima D, Kunishima I. High-density chain ferroelectric random access memory (chain FRAM). J Solid-State Circ, 1998. 33: 787–792

    Article  Google Scholar 

  35. Koo J M, Seo B S, Kim S, et al. Fabrication of 3D trench PZT capacitors for 256 Mbit FRAM device application. In: International Electron Device Meeting (IEDM), session 14-2, 2005. 351–354

  36. Kanaya H, Tomioka K, Matsushita T, et al. A 0.602 μm2 nestled chain cell structure formed by one mask etching process for 64 Mbit FeRAM. In: VLSI Symposia on Technology, session 15-3, 2004. 150–151

  37. Shimojo Y, Konno A, Nishimura J, et al. High-density and high-speed 128 Mb chain FeRAMTM with SDRAM-compatible DDR2 interface. In: VLSI Symposia on Technology, session 11B-1, 2009. 218–219

  38. Han J P, Ma T P. Ferroelectric-gate transistor as a capacitor-less DRAM cell. Integrat Ferroelectr, 1999, 27: 1053–1062

    Google Scholar 

  39. Yuasa S, Nagahama T, Fukushima A, et al. Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions. Nat Mater, 2004, 3: 868–871

    Article  Google Scholar 

  40. Durlam M, Addie D, Akerman J, et al. A 0.18 μm 4 Mb toggling MRAM. In: International Electron Device Meeting (IEDM), session 34-6, 2003. 995–997

  41. Prejbeanu I L, Kula W, Ounadjela K, et al. Thermally assisted switching in exchange-biased storage layer magnetic tunnel junctions. IEEE Trans Magnet, 2004, 40: 2625–2627

    Article  Google Scholar 

  42. Lee Y M, Yoshida C, Tsunoda K, et al. Highly scalable STT-MRAM with MTJs of top-pinned structure in 1T/1MTJ cell. In: VLSI Symposia on Technology, session 5-2, 2010. 49–50

  43. Ishigaki T, Kawahara T, Takemura R, et al. A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions. In: VLSI Symposia on Technology, session 5-1, 2010. 47–48

  44. Huai Y. Spin-transfer torque MRAM (STT-MRAM): challenges and prospects. AAPPS Bull, 2008, 18: 33–40

    Google Scholar 

  45. Hönigschmid H, Angerbauer M, Dietrich S, et al. A non-volatile 2 Mbit CBRAM memory core featuring advanced read and program control. In: VLSI Symposia on Circuits, session 13-2, 2006. 110–111

  46. Aratani K, Ohba K, Mizuguchi T, et al. A novel resistance memory with high scalability and nanosecond switching. In: International Electron Device Meeting (IEDM), session 30-5, 2007. 783–786

  47. Waser R. Electrochemical and thermochemical memories. In: International Electron Device Meeting (IEDM), session 12-1, 2008. 289–292

  48. Xu N, Gao B, Liu L F, et al. A unified physical model of switching behavior in oxide-based RRAM. In: VLSI Symposia on Technology, session 10-3, 2008. 100–101

  49. Chua L O. Memristor-the missing circuit element. IEEE Trans Circ Theory, 1971, 18: 507–519

    Article  Google Scholar 

  50. Strukov D B, Snider G S, Stewart D R, et al. The missing memristor found. Nature, 2008, 453: 80–83

    Article  Google Scholar 

  51. Borghetti J, Snider G S, Kuekes P J, et al. ’Memristive’ switches enable ’stateful’ logic operations via material implication. Nature, 2010, 464: 873–876

    Article  Google Scholar 

  52. Kozicki M N, Balakrishnan M, Gopalan C, et al. Porgrammable metallization cell memory based on Ag-Ge-S and Cu-Ge-S solid electrolytes. In: 2005 Non-volatile Memory Technology Symposium, 2005. 83–89

  53. Sakamoto T, Tada M, Banno N, et al. Nonvolatile solid-electrolyte switch embedded into Cu interconnect. In: VLSI Symposia on Technology, session 6B-4, 2009. 130–131

  54. Lin Y Y, Lee F M, Chen Y C, et al. A novel TiTe buffered Cu-GeSbTe/SiO2 electrochemical resistive memory (ReRAM). In: VLSI Symposia on Technology, session 8-4, 2010. 91–92

  55. Da Silva J L F, Wei S H, Zhou J, et al. Stability and electronic structures of CuxTe. Appl Phys Lett, 2007, 91: 091902–091904

    Article  Google Scholar 

  56. Cabral C, Chen K N, Krusin-Elbaum L, et al. Irreversible modification of Ge2Sb2Te5 phase change material by nanometer-thin Ti adhesion layers in a device-compatible stack. Appl Phys Lett, 2007, 90: 051908–0511910

    Article  Google Scholar 

  57. Chen A, Haddad S, Wu Y C J, et al. Non-volatile resistive switching for advanced memory applications. In: International Electron Device Meeting (IEDM), session 5-5, 2005. 746–749

  58. Wang M, Luo W J, Wang Y L, et al. A novel CuxSiyO resistive memory in logic technology with excellent data retention and resistance distribution for embedded applications. In: VLSI Symposia on Technology, session 8-3, 2010. 89–90

  59. Sakotsubo Y, Terai M, Kotsuji S, et al. A new approach for improving operating margin of unipolar ReRAM. In: VLSI Symposia on Technology, session 8-2, 2010. 87–88

  60. Baek I G, Lee M S, Seo S, et al. Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses. In: International Electron Device Meeting (IEDM), session 23-6, 2004. 587–590

  61. Lee H Y, Chen P S, Wu T Y, et al. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM. In: International Electron Device Meeting (IEDM), session 12-3, 2008. 297–300

  62. Ho C H, Lai E K, Lee M D, et al. A highly reliable self-aligned graded oxide WOx resistance memory: conduction mechanisms and reliability. In: VLSI Symposia on Technology, session 12B-2, 2007. 228–229

  63. Chien W C, Chen Y C, Lai E K, et al. Unipolar switching behaviors of RTO WOx RRAM. IEEE Electr Device Lett, 2010, 31: 126–128

    Article  Google Scholar 

  64. Chen Y C, Chien WC, Lin Y Y, et al. Cu-based and WOx-based resistive switching memories (ReRAMs) for embedded and stand-alone applications. In: International Conference on Solid-State and Integrated-Circuit Technology, 2010. invited

  65. Chien W C, Chen Y C, Lee F M, et al. A novel Ni/WOX/W ReRAM with excellent retention and low switching current. In: 2010 International Conference on Solid State Devices and Materials (SSDM), 2010. 1104–1105

  66. Lai E K, Chien W C, Chen Y C, et al. Tungsten oxide resistive memory using rapid thermal oxidation of tungsten plugs. Japan J Appl Phys, 2010, 49: 04DD17–04DD17-4

    Article  Google Scholar 

  67. Chien W C, Chen Y C, Lai E K, et al. High-speed multilevel esistive RAM using RTO WOx. In: 2009 International Conference on Solid State Devices and Materials (SSDM), session G-7-3, 2009. 1206–1207

  68. Lee M J, Lee C B, Kim S, et al. Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates. In: International Electron Device Meeting (IEDM), session 4.4, 2008. 85–88

  69. Chevallier C J, Chang H S, Lim S F, et al. A 0.13 μm 64 Mb multi-layered conductive metal-oxide memory. In: 2010 International Solid-State Circuit Conference Digest (ISSCC), session 14-3, 2010. 260–261

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  1. Macronix International Co., Ltd., 16 Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan, 300, China

    ChihYuan Lu, HangTing Lue & YiChou Chen

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  1. ChihYuan Lu
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  2. HangTing Lue
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  3. YiChou Chen
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Correspondence to ChihYuan Lu.

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Lu, C., Lue, H. & Chen, Y. State-of-the-art flash memory devices and post-flash emerging memories. Sci. China Inf. Sci. 54, 1039–1060 (2011). https://doi.org/10.1007/s11432-011-4221-z

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