Abstract
This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.
Similar content being viewed by others
References
Boneh, D., Demillio,R., Liotin, R.: On the importance of checking crypto-graphic protocols for fault. In: EUROCRYPT 1997, LNCS, vol. 1233, pp. 37–51. Springer, Berlin (1997)
Yen S.M., Joye M.: Checking before output may not be enough against fault-based cryptanalysis. IEEE Trans. Comput. 49(9), 967–970 (2000)
Biham E., Shamir A.: Differential fault analysis of secret key cryptosystems. CRYPTO 1294, 513–525 (1997)
Clavier C.: Secret external encodings do not prevent transient fault analysis. LNCS 4727, 181–194 (2007)
Bar-El, H., Choukri, H., Naccache, D., Tunstall, M., Whelan, C.: The sorcerer’s apprentice guide to fault attack. IACR ePrint archive, vol. Report 2004/100, pp. 1–13 (2004)
Kim C.H., Quisquater J.-J.: Faults, injection methods, and fault attacks. IEEE Design Test Comput. 24, 544–545 (2007)
Guilley, S., Sauvage, L., Danger, J.-L., Selmane, N., Pacalet, R.: Silicon-level solutions to counteract passive and active attacks. In: Proceedings of the 5th Workshop on Fault Diagnosis and Tolerance in Cryptography, pp. 3–17 (2008)
Endo, S., Sugawara, T., Homma, N., Aoki, T.: An on-chip glitchy-clock generator and its application to safe-error attack. In: 2nd International Workshop on Constructive Side-channel Analysis and Secure Design–COSADE, pp. 175–182 (2011)
Fukunaga, T., Takahashi, J.: Practical fault attack on a cryptographic lsi with iso/iec 18033-3 block ciphers. In: Proceedings of the 6th Workshop on Fault Diagnosis and Tolerance in Cryptography, pp. 84–92 (2009)
Side-channel Attack Standard Evaluation Board. http://www.rcis.aist.go.jp/special/SASEBO/
Amiel, F., Villegas, K., Feix, B., Marcel, L.: Passive and active combined attacks: combining fault attacks and side channel analysis. In: Proceedings of the 4th Workshop on Fault Diagnosis and Tolerance in Cryptography, pp. 92–102 (2007)
Li Y., Sakiyama K., Gomisawa S., Fukunaga T., Takahashi J., Ohta K.: Fault Sensitivity Analysis. Workshop on Cryptographic Hardware and Embedded Systems-CHES. LNCS 6225, 320–334 (2010)
Coron, J.S.: Resistance against differential power analysis for elliptic curve cryptosystems. In: CHES 1999, LNCS, vol. 1717, pp. 292–302. Springer, Berlin (1999)
Menezes J.A., Oorschot C.P., Vanstone A.S.: Handbook of Applied Cryptography. Boca Raton, CRC Press (1997)
Miyamoto, A., Homma, N., Aoki, T., Satoh, A.: Systematic design of high-radix montgomery multipliers for rsa processors. In: Proceedings of the 26th IEEE International Conference on Computer Design, pp. 416–422 (2008)
Homma N., Miyamoto A., Aoki T., Satoh A., Shamir A.: Comparative power analysis of modular exponentiation algorithms. IEEE Trans. Comput. 59(6), 795–807 (2010)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Endo, S., Sugawara, T., Homma, N. et al. An on-chip glitchy-clock generator for testing fault injection attacks. J Cryptogr Eng 1, 265–270 (2011). https://doi.org/10.1007/s13389-011-0022-y
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s13389-011-0022-y