Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements

Abstract

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) computations involve quite a large number of complex multiplications and complex additions. Optimizing the FFT processing elements in terms of complex multiplication reduces area and power consumption. In this paper, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers. Approximate arithmetic computation appears to be effective solution for the systems that exhibit an intrinsic error tolerance. The computational errors arising because of approximation can be considered as trade-off for the significant gains in power and area. Approximate 8- and 16-bit multipliers are used in radix-2 butterfly unit which is the crucial computational component in FFT/IFFT processing. The designed FFT/IFFT processing units are analyzed, synthesized and simulated in Altera Cyclone II EP2C35F672C6 Field Programmable Gate Array (FPGA) device. Experimental results show that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area and power efficiency of 33.47% and 1.8% respectively compared to accurate 16-point FFT processor. The 8-point and 16-point Decimation In Time (DIT)—FFT incorporating approximate computational elements operate at a speed of 26.69 Gbps and 46.20 Gbps, respectively.