Copper metallization for advanced IC: requirements and technological solutions
Introduction
With increase in density, interconnect dimensions are decreased and the number of metal levels is raised. This will led to an increase of interconnect parasitics. Particularly the delay (expressed as RC) of the metal lines will become a limitation for the running of high speed circuits.
The use of low-k and/or low-resistivity materials is a way to limit the interconnect contribution to the parasitics. In the following, after an analysis of the critical electrical parameters, we will present the integration of copper in a dual damascene architecture. The specific aspects of this reverse architecture will be discussed. First the dual damascene structure construction will be presented. The metal CMP process, and its impact on electrical performance, will then be discussed. The reliability performance of copper lines will finally be shown.
Section snippets
Requirements for advanced interconnects
The general SIA road map for interconnects is presented in Table 1. The detrimental effect of the interconnect on the circuit performance is due to the decrease of the metal pitch which will lead to an increase of both line resistance and capacitance. While the resistance increase will influence the delay (RC) and the voltage drop (RI) the interconnect capacitance will also increase the power consumption (CV2f) and the crosstalk sensitivity (CdV/dt) [2]. As shown in Fig. 1, when decreasing the
Structure construction
Two constructions are compared (Fig. 4) [5], [6]: for the self-aligned architecture an embedded counter mask is used to define the via holes. One advantage is that the lines are defined on a nearly flat substrate; one difficulty is to reach a high selectivity between the hard mask material (SiN) and the SiO2 [7]. The via first architecture is characterised by a very thin intermediate hard mask, the thickness of which can be decreased down to zero. Within the range of SiN hard mask thickness
Conclusion
We have presented an overview of the main requirements and issues on copper metallization for advanced interconnects. For copper deposition, various techniques allowing good film properties are suitable for trench and via filling. However, the copper/barrier interface seems to be responsible of variations in electromigration life time. Due to the great impact on via resistance and reliability, barrier materials still need to be improved. One of the most critical issues of the copper integration
Acknowledgements
This work has been carried out in collaboration with the GRESSI consortium between CEA-LETI and France Telecom-CNET. EC funding within the ESPRIT 25220 DAMASCENE project is acknowledged.
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