A beam-forming transmit ASIC for driving ultrasonic arrays

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Abstract

This paper describes the design of a programmable eight-channel application specific integrated circuit (ASIC) for driving ultrasonic array transducers. The ASIC is capable of generating variable delay lengths of up to 65 μs in steps of 1 ns. Integrated on the same chip is an array of eight high-voltage pulser circuits (up to 100 V). The output pulse width can also be set to match the transducer operating frequency. A minimum width of 20 ns is possible and the rise and fall times are typically 5 and 7 ns. It can also be programmed to give bursts of up to 16 repetitions to facilitate Doppler imaging.

Introduction

The use of arrays of ultrasonic transducers is widespread in medical ultrasonic imaging. In general, these are 1D arrays of piezo ceramic composite materials, although PVDF arrays have been reported [1]. By electrically exciting the array elements in a pre-determined order, it is possible to electronically steer a focused beam of ultrasonic energy for imaging purposes [2]. Recent years have seen the emergence of 2D arrays that facilitate 3D ultrasound imaging [3]. Although in the main, these are sparse arrays, the trend is for the number of array elements that have to be driven to continuously increase. The implication is that the wire bundle that connects the transducer array to the control unit becomes ever more unwieldy. A solution to this problem is to mount as much of the control electronics, both transmit and receive as possible at the array itself. This paper describes an eight-channel prototype transmit beam-forming IC that can be mounted directly on the transducer head.

Section snippets

Overview of the new IC

The transmit electronics play a crucial role in determining the firing sequence of the transducer array and consequently the steering and focusing of the ultrasonic beam. This task requires electronics capable of generating delays of variable length and producing high-voltage output pulses to excite the ultrasonic transducer.

A programmable prototype transmit electronics integrated circuit has, therefore, been designed. The prototype IC has eight independent channels, each of which is

Fine timing block

The central component of the fine timing circuitry is a DLL which is used to interpolate between successive periods of a reference clock [4]. Fig. 2 shows the basic block diagram of the DLL. A reference clock is delayed through a variable delay line until it is synchronised with the next period of the reference clock. A feedback loop constantly adjusts the delay so that the phase difference between the two clocks remains zero.

Pulse control block

The pulse control block allows for the programmability of the chip’s output. It is possible to vary the width of the output pulse to match the transducer’s operating frequency. This is achieved by controlling the charging current to a capacitor in a one-shot (monostable) circuit. The charging current is controlled by means of a programmable current-source. The time constant of the one-shot circuit is then determined solely by the ratio of its capacitor value (in this case 1 pF) to the controlled

High-voltage output stage

This chip integrates the high-voltage pulsing circuits along with the 5 V CMOS digital circuits. The technology is provided by the Alcatel Mietec Intelligent Interface Technology (I2T) which permits the co-integration of CMOS, bipolars (BiCMOS) and DMOS technologies. The pulser, shown in Fig. 9 is configured as a source-follower. Co-integrated DMOS transistors are used as they can sustain the 100 V needed to drive the array elements. The output must remain at ground during the idle state for

Floorplanning for the ASIC

The floorplanning and layout as shown in the photomicrograph of Fig. 11, was performed using the Cadence Block Ensemble and Cell Ensemble. The 5 V digital circuits occupy the top half of the silicon. Eight identical timing channels occupy the first row of the chip. The second row has a shielded (from digital switching) analogue current source. It has a separate pair of supply and ground rails to minimise noise pick-up. The DLL is in the middle as equal distribution of parasitic capacitance is

Conclusion

A new eight-channel prototype transmit electronics ASIC for ultrasonic imaging systems has been designed. The IC is capable of generating variable delay length up to 65 μs in steps of 1 ns. Integrated on the same chip is an array of eight high-voltage pulser circuits (up to 100 V). The output pulse width can be squeezed down to 20 ns and it can also be programmed to give up to a 16 repetitive pulse burst.

John V. Hatfield received the BSc degree in physics from the University of Leeds, Leeds, UK, in 1973 and the MSc degree from the University of Manchester, Institute of Science and Technology (UMIST), Manchester, UK, in 1984. He received the PhD degree from the same university in 1988 for his researches into position-sensitive particle detectors. Currently, he is a reader in the Department of Electrical Engineering and Electronics at UMIST. His research interests are in the field of integrated

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John V. Hatfield received the BSc degree in physics from the University of Leeds, Leeds, UK, in 1973 and the MSc degree from the University of Manchester, Institute of Science and Technology (UMIST), Manchester, UK, in 1984. He received the PhD degree from the same university in 1988 for his researches into position-sensitive particle detectors. Currently, he is a reader in the Department of Electrical Engineering and Electronics at UMIST. His research interests are in the field of integrated sensors and transducers and he has published more than 70 papers in this area.

Kwet Seng Chai was awarded the BE degree in electronic engineering by the University of Manchester Institute of Science and Technology in 1995. He was awarded an MPhil degree in the following year for a current-mode analogue IC design project on a charged particle detecting integrated circuit. He was then employed as a research assistant working on an EU funded project for the development of 2D ultrasonic arrays. He was awarded the PhD for this work, by UMIST, in the year 2000. Currently, he is employed as an IC design engineer by Analog Devices in the UK.

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