Elsevier

Computer Networks

Volume 78, 26 February 2015, Pages 4-25
Computer Networks

A new power profiling method and power scaling mechanism for energy-aware NetFPGA gigabit router

https://doi.org/10.1016/j.comnet.2014.10.036Get rights and content

Abstract

Today the ICT industry accounts for 2–4% of the worldwide carbon emissions that are estimated to double in a business-as-usual scenario by 2020. A remarkable part of the large energy volume consumed in the Internet today is due to the over-provisioning of network resources such as routers, switches and links to meet the stringent requirements on reliability. Therefore, performance and energy issues are important factors in designing gigabit routers for future networks. However, the design and prototyping of energy-efficient routers is challenging because of multiple reasons, such as the lack of power measurements from live networks and a good understanding of how the energy consumption varies under different traffic loads and switch/router configuration settings. Moreover, the exact energy saving level gained by adopting different energy-efficient techniques in different hardware prototypes is often poorly known. In this article, we first propose a measurement framework that is able to quantify and profile the detailed energy consumption of sub-components in the NetFPGA OpenFlow switch. We then propose a new power-scaling algorithm that can adapt the operational clock frequencies as well as the corresponding energy consumption of the FPGA core and the Ethernet ports to the actual traffic load. We propose a new energy profiling method, which allows studying the detailed power performance of network devices. Results show that our energy efficient solution obtains higher level of energy efficiency compared to some existing approaches as the upper and lower bounds of power consumption of the NetFPGA Openflow switch are proved to be 30% lower than ones of the commercial HP Enterprise switch. Moreover, the new switch architecture can save up to 97% of dynamic power consumption of the FPGA chip at lowest frequency mode.

Introduction

Nowadays networked applications such as cloud computing, social networks as well as multimedia services have become ubiquitous. The deployment of broadband networking infrastructure in the core and data centers at the edge of the networks has become very common in recent years. Consequently, the ICT industry accounts for 2–4% of the worldwide carbon emissions that are estimated to double in a business-as-usual scenario by 2020 [1]. However, until recently, ICT has not sufficiently applied energy-efficient concepts, even in fast growing sectors like telecommunications and the Internet. Backbone networks nowadays are specifically designed to be extremely over dimensioned in terms of switching capacity and number of deployed links and nodes in order to guarantee zero-loss and minimum latency packet forwarding [2], [3]. When taking a closer look at the network components, the energy consumption of current network devices is substantially flat and almost independent of their actual workloads. Thus, the large volume of energy consumed in the network infrastructure results in high operational expenses and environmental pollution.

For these reasons the concept of green networking has become increasingly important and received considerable attention from research and industrial communities. It focuses on different research issues, including designing more energy efficient technologies inside physical network components, deploying energy-efficient methods in network architecture and control, energy-aware traffic engineering and routing and so forth. Among these methods, one research direction is to re-design the physical hardware architecture of routers with energy-efficient concepts, as switches and routers consume most energy in the Internet [4], [5]. However, making such kinds of network devices more energy-efficient is challenging because of several difficulties:

  • Firstly, the detailed energy consumption in different sub-components of a router under different traffic load and network configuration settings is usually not well understood. This is because of the lack of analytical tools and power measurement methods in live networks.

  • Secondly, it is difficult to deploy different energy-aware concept in a real network device, as commercial routers do not offer sufficient flexibility and mechanisms for prototyping and implementing novel energy-optimized network algorithms.

  • Although there are several proposed strategies for energy-aware switches and routers recently, such as dynamic adaptation of the link rates [6], [7] or smart sleeping [2], [8], the exact energy saving by adopting these techniques is poorly known. The reason is that the energy-saving level depends very much on specific hardware implementation and the type of routers (number of ports, the type of CPU used, etc.).

In this research we try to answer one important issue in the design of energy-aware router architectures, which is how to optimize the energy volume consumed by a router proportionally to its actual traffic load. As illustrated in Fig. 1, in the ideal case, the energy consumption of a network device should be proportional to its traffic load. That is, energy consumption in a low utilization scenario should be much lower than in case of high traffic utilization. However, in the Internet today, redundant or lightly utilized links and devices usually consume nearly as much energy as devices that are switching large volumes of traffic do [9].

In this article, we first analyze the power performance of sub-components in the NetFPGA-based OpenFlow gigabit router documented in [10]. We then propose a new power-scaling method for the FPGA that remarkably reduces the energy consumption, and propose a new method for detailed power profiling of network devices. The main contributions of our work are the followings:

  • A measurement framework for quantifying and profiling the detailed energy1 consumption of sub-components in the NetFPGA OpenFlow switch. Based on the detailed energy profile, the behavior of the switch in terms of energy consumption under various traffic utilization scenarios and network configuration settings has been studied and well understood.

  • A new power scaling mechanism fully embedded on the FPGA chip which is able to adapt the operations of the FPGA core and the link capacities of each Ethernet port individually to the real-time traffic load. Although the deployment of the new mechanism is not done on a commercial router, our purpose is to prove that the energy performance of a network device can greatly be improved by re-optimizing the existing hardware resources.

  • An analytic model based on the detailed energy profile, which calculates the bounds on minimum, maximum and average energy consumption of network devices under different traffic utilization. The model can be used as a framework to evaluate the energy performance of a router.

  • Based on the proposed power profiling method, we study the power profile of the new developed energy-aware OpenFlow switch and compare its energy efficiency with some commercial energy aware switches. Analytical and measurement results show that our concept obtains higher level of energy efficiency compared to some existing approaches [11], [12].

The rest of the article is organized as follows. In Section 2, current work related to energy-efficient networking as well as current approaches for energy-aware gigabit routers is discussed. We focus on the measurement framework for profiling the energy consumption of the NetFPGA in Section 3. The detailed energy profile of the NetFPGA gigabit router is also given in this section. Section 4 proposes a new power scaling mechanism for the NetFPGA router and presents the corresponding energy consumption of the router when operating in different modes. Section 5 shows the performance evaluation of the new developed energy-aware functionalities. Conclusions are drawn in Section 6.

Section snippets

Related work

As already discussed in Section 1, the difference in the energy consumption of current network devices between highly loaded and idle states is not much. In other words, most of the network devices today are not energy-efficient. In this research, we focus on improving energy efficiency of a router by adapting its energy consumption proportionally to its traffic load.

The concept of energy proportionality is introduced by the work of Mahadevan et al. [9] and Heller et al. [13], which states that

Profiling energy consumption on NetFPGA

In order to study the energy consumption of the NetFPGA gigabit router, we set up a measurement test-bed. The test-bed allows us to measure and profile the energy consumption of various functional components on the NetFPGA board in detail. Based on the measurement we are able to develop different energy-optimization strategies on hardware and investigate the effect of these methods on the energy performance of the device. In this section, we describe the efforts in building the benchmark

Full power scaling mechanism on NetFPGA

Based on the power profile presented in the previous section, we developed a new energy-aware OpenFlow switch prototype. Different from some previous approaches that adapt the clock frequencies in some parts of the NetFPGA [11], [12], our focus is to reduce the energy consumption of both the Ethernet module and the NetFPGA chip. Our basic idea is to adapt the operating clock frequencies of the FPGA chip and the link rates of the 4 Ethernet ports individually based on the actual traffic load,

Performance evaluation

In this section we present the performance evaluation on the experimental results obtained based on the experiment setup presented in Section 3.1.

Conclusions

In this article, we firstly develop a new NetFPGA OpenFlow gigabit router based on power scaling mechanisms. By changing the operation clock frequencies of the FPGA core and 4 gigabit Ethernet interfaces individually, the switch is able to reduce the power consumption up to 60.2%. Moreover, the power consumption of different functional blocks on the router has been researched based on the test-bed specifically designed for power modeling purposes. Among the functional blocks, the additional

Pham Ngoc Nam received B. Eng. Degree In Electronics and Telecommunications from Hanoi University of Science and Technology (Vietnam) and M.Sc. degree in Artificial Intelligence from K.U. Leuven (Belgium) in 1997 and 1999, respectively. He was awarded a Ph.D. degree in Electrical Engineering from K.U.Leuven in 2004. From 2004 until now he has been working at Hanoi University of Science and Technology, Vietnam. His research interests include QoS management for multimedia applications,

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    Pham Ngoc Nam received B. Eng. Degree In Electronics and Telecommunications from Hanoi University of Science and Technology (Vietnam) and M.Sc. degree in Artificial Intelligence from K.U. Leuven (Belgium) in 1997 and 1999, respectively. He was awarded a Ph.D. degree in Electrical Engineering from K.U.Leuven in 2004. From 2004 until now he has been working at Hanoi University of Science and Technology, Vietnam. His research interests include QoS management for multimedia applications, reconfigurable embedded systems and low-power embedded system design.

    Nguyen Huu Thanh received BEng and MSc degrees in Electrical Engineering from Hanoi University of Science and Technology (Vietnam) in 1993 and 1995, respectively. He was awarded a PhD degree with summa cum laude in Computer Science from the University of Federal Armed Forces Munich (Germany) in 2002. In 2002 he joined Fraunhofer FOKUS in Berlin and worked on the areas of QoS-guarantees for multimedia in overlay networks. From 2004 until now he has been working for Hanoi University of Science and Technology, Vietnam. His research focuses on mobility, QoS/QoE and resource management of wireless broadband networks, new service platforms for future networks, Software-Defined Networking and the Future Internet.

    Vu Quang Trong received B. Eng. degree in Electronics and Telecommunications from Hanoi University of Science and Technology (Vietnam) in 2013. Since 2010, he has been working at the Embedded System and Reconfigurable Computing Laboratory, HUST. His research interests include energy-efficient networking, reconfigurable embedded systems and low-power embedded system design.

    Tran Hoang Vu is a Ph.D. student in Electrical Engineering of Hanoi University of Science and Technology (Vietnam), where he has been since 2010. He received B. Eng. degree in Electronics and Telecommunications from Da Nang University of Technology and M.Sc. degree from the University of Danang (Vietnam) in 2004 and 2008, respectively. From 2004 until now he has been working at Danang College of Technology-The University of Danang, Vietnam. His research interests include Reducing power consumption of Data Center Networks, reconfigurable embedded systems and low-power embedded system design

    Thu-Huong Truong got her Bachelor degree of Electronics and Telecommunications in 2001 from Hanoi University of Science and Technology (HUST), where she is currently giving lecture and doing research. Being funded in by DAAD—the German Government Fund, she then achieved her master degree in Information and Communication Systems from the Technical University of Hamburg-Harburg (TUHH), Germany, in 2004. From 2004 till 2007, she pursued her Ph.D. career at University of Trento, Italy. Her educational, research, and development work is oriented toward next generation networks, protocols and mechanism, traffic analyses, QoE/QoS measuring, green networking and deployment of new integrated multimedia services into fixed and mobile networks.

    Phuoc Tran-Gia is professor and director of the Chair of Communication Networks, University of Würzburg, Germany. He is also Member of the Advisory Board of Infosim (Germany) specialized in IP network management products and services. Prof. Tran-Gia is also cofounder and board member of Weblabcenter Inc. (Dallas, Texas), specialized in Crowdsourcing technologies. Previously he was at academia in Stuttgart, Siegen (Germany) as well as at industries at Alcatel (SEL) and IBM Zurich Research Laboratory. He is active in several EU framework projects and COST actions. Prof. Tran-Gia was coordinator of the German-wide G-Lab Project ‘National Platform for Future Internet Studies’ aiming to foster experimentally driven research to exploit future Internet technologies. His research activities focus on performance analysis of the following major topics: Future Internet & Smartphone Applications; QoE Modeling & Resource Management; Software Defined Networking & Cloud Networks; Network Dynamics & Control; Crowdsourcing. He has published more than 100 research papers in major conferences and journals and received the Fred W. Ellersick Prize 2013 (IEEE Communications Society).

    Christian Schwartz received his Diploma degree in Computer Science from the University of Würzburg in 2010. Since October 2010, he is working towards his PhD at the Chair of Communication Networks in Würzburg. His main research interests include the modelling and optimization of energy efficiency in both mobile networks and data centers. Additionally, he is interested in the analysis of problems caused by signalling in mobile networks.

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