Designing a 2-to-4 decoder on nanoscale based on quantum-dot cellular automata for energy dissipation improving

Abstract

Quantum dot Cellular Automata (QCA) as a new architecture at the nanoscale is developed as a feasible alternative for the existing Complementary Metal–Oxide–Semiconductor (CMOS) designs. The decoder in the QCA is a very important circuit to address the QCA-based random access memory arrays. It plays a key role in many circuit designs, such as Controlled Logic Block (CLB), Field Programmable Gate Array (FPGA), and memory circuits’ designs. In this paper, a five-input majority gate is used in a modular design methodology to design a 2-to-4 decoder in QCA. The proposed 2-to-4 QCA-based decoder can be utilized to synthesize n-to-2ⁿ decoders as well. The functional correctness of the proposed circuit is evaluated using QCADesigner tool. Also, QCAPro simulator as a popular power estimator tool in QCA evaluates the power dissipation. The obtained results have shown the significant success in terms of clock speed (%57), wire-crossing (%33), cell number (%27), area (%26) and power dissipation than the existing designs.

Introduction

Quantum-dot Cellular Automata (QCA) was proposed by Lent in 1993 [1]. Low power, high density, and regularity are considered for its performance. Also, it presents a new device architecture for nanotechnology [2,3]. Cells are made up of four quantum dots along corners of a square with two electrons. The two possible arrangements signify logic 0 or logic 1 [4,5]. The Columbic interactions with neighboring cell states define the position of the cell [5,6]. Circuits occupy smaller area using QCA technology compared to Complementary Metal-Oxide-Semiconductor (CMOS). Thus, they stand as a good substitute to the CMOS technology [7]. The power consumption is significantly less than conventional CMOS circuits because of electrical current absence in QCA computations. The power consumption issue of the circuits has been ignored in many QCA logical and arithmetic designs [8].

On the other hands, the decoder is a circuit that modifies a code into a set of signals. The line decoder is considered as a type of decoder, which receipts an n-digit binary number and decodes it into 2n data lines. The 1-to-2 decoder is considered as the simplest. There is a procedure to design larger line decoders. Smaller decoders just like other digital circuits should combine together for making larger decoders. An alternative circuit for the 2-to-4 line decoder which is changing the 1-to-2 decoders with their circuits will show that both circuits are alike. In a similar fashion, a 3-to-8 decoder can be designed based on 1-to-2 and 2-to-4 decoders, and a 4-to-16 decoder can be designed based on two 2-to-4 decoders. The selection among multiple devices is done through a line decoder circuit [9]. Decoders play an important role in circuit designs, such as carrying out of a Field Programmable Gate Array (FPGA), Controlled Logic Block (CLB) and memory circuits designs [10]. The optimization of a power consumption in the modular decoder is not mentioned properly in the literature although the decoder has an important role in QCA-based designs. A modular design method for the QCA-based decoder is proposed in this paper to improve the power consumption. Briefly, the important features of this work are as follows:

• A modular QCA-based decoder is designed and its efficiency in realizing n to 2n decoders (n > = 2) is explored.

• A one-level architecture with tree clocks for reducing the energy consumption of the QCA-based decoder is proposed.

• The analysis of the offered design in terms of wire-crossings, delay, number cell, and area are reported.

This paper is organized as follows: Section 2 reviews the related work and basic terminologies. Section 3 provides the design of the proposed decoder. The proposed decoder is simulated and evaluated in Section 4. Conclusions and future studies are discussed in the last section.