A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

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Abstract

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.

Introduction

The CMOS transistor gate length scaling is projected to continue through 2016 down to the incredible 9 nm [1]. Even if these dimensions can be realized using technological innovations, CMOS devices will suffer from a number of short channel effects, such as the threshold voltage roll-off, the drain induced barrier lowering (DIBL) and the subthreshold swing all of which degrade the MOSFET performance. A number of solutions have been proposed to overcome these problems [2]. Employing a double gate field effect transistor (DG MOSFET) structure instead of using bulk-Si transistors is one of these solutions. In addition to the inherent suppression of SCEs, DG MOSFETs offer high drive current and transconductance [3]. More importantly, the electrical coupling between the two gates results in high Ion/Ioff ratios when the threshold voltage is properly controlled [4], [5].

An ultra shallow extended source/drain is another effective method to suppress SCEs. But, it is very difficult to form shallow junctions by conventional fabrication techniques. However, it has been reported that SCEs can be suppressed by using an inversion layer as an ultra shallow extended S/D [6], [7], [8], [9], [10], [11], [12]. These devices are known as electrically variable shallow junction MOSFETs (EJ MOSFETs). In spite of the area penalty associated with these devices due to the additional side gates required for the inversion layer formation, EJ MOSFETs are expected to play a major role in the reduction of SCEs and hot carrier effects as discussed in our paper. To combine the advantages of both DG and EJ structures, in this paper we propose a novel symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain regions. This structure is similar to that of a symmetrical DG MOSFET with the exception that the front gate consists of two asymmetrical side gates on both sides of the main gate. The aim of this paper is, therefore, to present the design and performance considerations of the proposed structure using two-dimensional simulation [13]. First, we have compared the performance of the EJ-DG structure with the symmetrical double gate (S-DG) structure in terms of threshold voltage, subthreshold swing, and electric field. Second, we have investigated the side gate design considerations in terms of threshold voltage, electric field, and hot carriers effects. Based on our simulation results, we demonstrate that the proposed EJ-DG structure is superior to the symmetrical double gate (S-DG) structure in controlling the SCEs.

Section snippets

EJ-DG structure

A schematic cross-sectional view of EJ-DG MOSFET implemented using the 2-D device simulator MEDICI is shown in Fig. 1. The front gate consists of two side gates using n+-poly and a main gate using p+-poly while the back gate is a p+-poly gate. The doping in the silicon thin film is kept at 1015 cm−3 (i.e., lightly doped with NA < 1016 cm−3 [14]) to avoid adverse effects associated with heavy doping, such as the mobility degradation [15] and the random microscopic fluctuations of dopant atoms [16].

Results and discussion

Fig. 2 shows a typical MEDICI simulated 2-D electron density distribution from source to drain of the EJ-DG structure for the main gate voltage VMGS = 0 V, the side gate voltage VSGS = 1.5 V and the drain to source voltage VDS = 0 V. As can be seen from the figure, the electron distribution in the channel region under the side gates decreases exponentially (linearly in the log scale) from the top of the silicon film to its bottom. Due to the difference between the work functions of the side gates and

Conclusions

In this paper, we have proposed a novel configuration for the symmetrical double gate SOI MOSFET using two side gates in order to investigate the influence of extremely shallow source and drain junctions on the short-channel effects. A constant voltage, independent of the main gate voltage, is applied to the side gates to form inversion layers acting as the extremely shallow virtual source and drain. Based on our simulation results we demonstrate that the combination of extremely shallow

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