Drive current boosting of n-type tunnel FET with strained SiGe layer at source

doi:10.1016/j.mejo.2008.02.020

Microelectronics Journal

Volume 39, Issue 12, December 2008, Pages 1671-1677

https://doi.org/10.1016/j.mejo.2008.02.020 Get rights and content

Abstract

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current ( $I_{OFF}$ ), its practical application is questionable due to low ON current ( $I_{ON}$ ) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in $I_{ON}$ . The enhancement in $I_{ON}$ is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An $I_{ON}$ of $\approx 0.58 mA / μ m$ and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the $I_{OFF}$ in fA range.

Introduction

The switching characteristics of the metal oxide semiconductor field effect transistor (MOSFET) have degraded considerably over the years due to relentless scaling. The subthreshold swing (S) of the MOSFET, which determines its switching characteristics and OFF current ( $I_{OFF}$ ) is un-scalable. Due to the drift-diffusion mode of carrier transport, the S in a MOSFET is theoretically limited to a value of 60 mV/decade at the room temperature. In fact, due to various short channel effects (SCEs), punchthrough, etc., the actual value of S in the present day MOSFET is much higher, which has resulted in an increase of $I_{OFF}$ from generation to generation and thus became a major concern for low-standby power (LSTP) applications. One therefore needs to explore novel device architectures which use other mode of carrier transport (i.e., impact ionization [1], interband tunneling [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], etc.) in order to achieve sub-60 mV/decade values of S. The impact ionization MOSFET (I-MOS) [1] appeared to be very promising due to its near ideal switching characteristics. However, due to problems like threshold voltage ( $V_{TH}$ ) shifts caused by hot carrier injection, non-rail to rail voltage swings and high operating voltage requirements, it failed to meet the ITRS [15] requirements for LSTP application.

The tunnel field effect transistor (TFET) with perfect saturation in the output characteristics has shown a lot of promise for achieving better scaling without severe SCEs [6]. Many variants of the TFET have been proposed till date. Among them, the vertical channel tunnel FET with a strained pseudomorphic $δ_{p^{+}}$ SiGe layer has been the most discussed structure. Due to its complex fabrication steps, routing (layouting) and packaging (not compatible with classical CMOS), Vertical channel TFET does not appear to be practically applicable for LSTP applications. To overcome above difficulties non-Si lateral Tunnel FET has been proposed by Baba [3] and Si lateral Tunnel FET has been proposed by Reddick [4], which enjoys CMOS compatible process steps. However, inspite of excellent subthreshold swing and high $I_{ON} / I_{OFF}$ ratio, the very low $I_{ON}$ is the main issue with this device. Recently, ON current improvement in this lateral structure has been reported using high- $κ$ gate dielectric in a double gate structure [16]. However, it does not take into account the mobility degradation related to high- $κ$ material, gate dielectric breakdown due to high field across the very thin high- $κ$ material and fabrication issues related to high- $κ$ material involved.

In this work, we propose a new classical-MOSFET-alike n-type tunnel FET architecture, which offers sub-60 mV/decade subthreshold swing with a significant improvement in $I_{ON}$ . The enhancement in $I_{ON}$ is achieved by introducing a thin strained SiGe layer on top of the silicon source. With the help of TCAD simulations, we have demonstrated that the proposed device is naturally immune to SCE and can be fabricated with standard CMOS process steps. It is observed that the body bias does not affect the drain current but the body current gets affected. Another original finding is that the introduction of strained SiGe layer makes the device immune to drain induced barrier lowering (DIBL) effect and the $I_{ON}$ increases exponentially with Ge mole fraction (x). It is noted that if proposed architecture is coupled with high- $κ$ material (as proposed in [16]) additional boost in drive current can be achieved with a thicker gate dielectric.

Section snippets

Device structure and working principle

The device being investigated is a lateral n-type tunnel FET with a strained SiGe layer on the top of the source. The tunnel FET is a gated reverse biased $p^{+} - p - n^{+}$ structure which uses the principle of gate controlled band to band tunneling (BTBT) for its operation. The proposed device is shown in Fig. 1. To operate the device, the $p^{+}$ source is grounded, and positive voltage (1 V) is applied to the $n^{+}$ drain with a positive sweep at gate. The working principle of conventional (without strained

Simulation models and device parameters

Two-dimensional device simulations are done with field dependent Kane's model [19] available in MEDICI [20] is used to model the BTBT generation and recombination rate. Kane's model has been shown to give a good match for BTBT in silicon based tunnel transistors at both high and low temperatures [4]. Since the source region is heavily doped, and tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also included in the simulations. Fermi Dirac statistics, although they

The strained SiGe layer

As discussed earlier, a strained SiGe layer is introduced at the top of the source in the conventional tunnel FET to achieve an improvement in the ON state current. Fig. 3(a) shows the effect of varying the Ge mole fraction (x) in the equilibrium band diagrams of the proposed device. As expected, the bandgap at the source end reduces as we increase the Ge mole fraction (x). This results in a reduction in the tunneling bandgap and consequently an increase in the transmission probability (Eq. (1)

Fabrication of the proposed device

One of different possible process flow compatible with standard CMOS process to fabricate the proposed device is shown in Fig. 12, which is the modification of metal gate MOSFET fabrication process proposed in [23]. It involves the following process steps, starting with Si wafer containing thin layer of strained SiGe( $\sim 20 nm$ ) on top: (i) shallow trench isolation (STI) formation, etch SiGe layer in the drain and channel region, grow Si in that region; (ii) dummy gate $({Si}_{3} N_{4} / poly - Si / {SiO}_{2})$

Conclusion

A novel planar silicon tunnel FET architecture with strained SiGe layer at source is proposed and analyzed using 2D device simulations. The proposed device is nearly free of SCE and DIBL and can be scaled upto channel lengths of 30 nm. The proposed device shows orders of improvement in ON current over the conventional TFET with the added advantage of compatibility with CMOS fabrication steps.

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View full text

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Abstract

Introduction

Section snippets

Device structure and working principle

Simulation models and device parameters

The strained SiGe layer

Fabrication of the proposed device

Conclusion

Surf. Sci.

Thin Solid Films

Solid State Electron.

J. Phys. Chem. Solids

Proposal for surface tunnel transistors

Jpn. J. Appl. Phys.

Silicon surface tunnel transistor

Appl. Phys. Lett.

Three-terminal silicon surface junction tunneling device for room temperature operation

IEEE Electron Device Lett.

Lateral interband tunneling transistor in silicon-on-insulator

Appl. Phys. Lett.

Band-to-band tunneling in carbon nanotube field-effect transistors

Phys. Rev. Lett.

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IEEE Trans. Electron. Devices