Elsevier

Microelectronics Journal

Volume 41, Issue 10, October 2010, Pages 616-626
Microelectronics Journal

Design of second-generation current conveyors employing bacterial foraging optimization

https://doi.org/10.1016/j.mejo.2010.06.013Get rights and content

Abstract

The present paper deals with the optimal sizing of CMOS positive second-generation current conveyors (CCII+) employing an optimization algorithm. A contemporary non-gradient stochastic optimization algorithm, called bacterial foraging optimization (BFO) algorithm, has been employed to obtain the optimal physical dimensions of the constituent PMOS and NMOS transistors of the CCII+. The optimization problem has been cast as a bi-objective minimization problem, where we attempt to simultaneously minimize the parasitic X-port input resistance (RX) and maximize the high end cut-off frequency of the current signal (fci). The results have been presented for a large selection of bias currents (I0) and our proposed algorithm could largely outperform a similar algorithm, recently proposed, employing particle swarm optimization (PSO) algorithm and also the differential evolution (DE) algorithm.

Introduction

Second-generation current conveyors were introduced in 1970 [1], [2] and gradually, over a period of time, they have gained immense popularity as a great candidate choice for current mode analog blocks. The current conveyors (CCs) are well-known analog current mode circuits (CMCs), which are abundantly used in amplifiers, oscillators, filters, wave shaping circuits etc. [3]. CCs enjoy great acceptance in the design of voltage and power starved circuits, as in medical electronics and space instrumentation, because of their low-voltage and low-power architectures. A CC is basically a three port (X, Y, Z) structure and it can be classified in accordance with the characteristics of its X, Y, and Z ports. CCs are also very popular in development of built-in self test (BIST) structures, used for the monitoring of currents in various branches of a circuit and are largely used as current sensors, used for the purpose of checking power supply current to ascertain health of a circuit [3]. For quite some time now, several research works have been primarily focused to obtain enhancement of the performances of these CCs fabricated. However, till now, it is strongly felt that the domain of designing high performance integrated CC circuits is still open and the need is ever growing in CMOS technology [4] where improving high end frequency response of current mode circuits is mostly appreciated.

In this paper, we focus on determination of optimal sizing of CMOS positive translinear loop second-generation current conveyors (CCII+) [4], [5], [6]. This automated design procedure strives to attain the optimal physical dimensions of all the PMOS and NMOS transistors employed in the physical realization of the CCII+. As mentioned in the previous paragraph, the design of a high performance CCII+ architecture requires that the bandwidth available for current signal should be as high as possible, i.e. one needs to maximize the high end cut-off frequency for the current waveform (fci). At the same time, another important factor is that the input resistance at port X i.e. RX is ideally zero, but always non-zero in practical realization. This RX must also be as small as possible. Hence the optimization problem is formulated as a bi-objective minimization problem, where we attempt to simultaneously minimize the parasitic input resistance RX and maximize the cut-off frequency fci. To the best of our knowledge and belief, few works have been reported till date, which focus on optimization of the physical dimensions of the CCII+, to attain enhanced performance [7], [8]. In [7], a steepest descent based optimization algorithm was used to iteratively adjust the W/L ratios and the capacitance values to obtain an optimum performance for the filter designed using CCII. In [8], a heuristic based iterative solution was proposed where, in each iteration, random solutions are generated and their suitabilities are evaluated utilizing some performance criteria. In this work, we propose to utilize bacterial foraging optimization (BFO) algorithm, a recently proposed stochastic non-gradient type optimization algorithm, to learn the desired physical dimensions of the MOS transistors, so that the desired objective is fulfilled to the maximum extent. The bi-objective minimization problem is solved employing the BFO algorithm, by utilizing a weighting approach, which combines the two conflicting objectives to produce a comprehensive objective function.

In BFO algorithm, the optimization strategy is based on the concept that for those animals which can locate, handle and ingest food better than other animals, the propagation of genes is favored and they are more likely to enter into a reproduction mechanism [9]. The algorithm works employing four stages: (i) chemotaxis, (ii) swarming, (iii) reproduction, and (iv) elimination and dispersal steps. It is the chemotactic behavior of E. coli bacteria which plays the most crucial part and requires efficient biomimicing to successfully evolve an optimization strategy. In the present work, we demonstrate how BFO can be successfully employed to determine the optimum design of second-generation current conveyors and we demonstrate how this algorithm could outperform a similar approach proposed in [10], where another popular non-gradient type optimization strategy, called particle swarm optimization (PSO), was employed to design an identical second generation current conveyor system and also differential evolution (DE) algorithm employed for the same design problem. To demonstrate the utility of the proposed system, the simulations were carried out for a large set of bias currents (I0) and in most of these cases BFO could emerge as the winning solution.

The rest of the paper is presented as follows. In section 2, we present a brief introduction of CMOS second generation current conveyors and their mathematical models employed for performing the necessary optimization function. Section 3 presents the bacterial foraging optimization algorithm employed in this work to obtain the optimal physical configurations of the NMOS and PMOS transistors. The performance evaluation is presented in section 4. Section 5 concludes the paper.

Section snippets

Second generation current conveyors and their mathematical models

Current conveyors were introduced in 1970 [1]. Nowadays, they form, arguably, the most famous building block in analog current mode circuits (CMCs) [2], [4]. It is a well-known fact that the voltage mode circuits (VMCs), like op-amps, voltage-to-frequency converters (VFCs), voltage comparators etc. are not suitable for high frequency operations, because of their constraints due to low bandwidths. Such problems arise in VMCs because of the presence of stray and circuit capacitances [3]. CMCs

The bacterial foraging optimization (BFO) algorithm

According to foraging theory, the animals search for and obtain nutrients in such a fashion that the energy intake per unit time is maximized, so that the animals get enough nutrient sources to survive and, at the same time, they can have spare time for other activities [9]. Hence, it is well-known that those animals which have poor foraging capability, get eliminated and those animals which have strong foraging capability, have their genes propagated for further reproduction procedure. An

Performance evaluation

The optimum values for the physical dimensions of the MOS transistors i.e. WN and LN values for each NMOS transistor and WP and LP values for each PMOS transistor are obtained for a series of bias current i.e. I0 values. For our simulations, the technology under consideration is CMOS AMS 0.35 μm, voltage supply specification is −2.5 V/+2.5 V. The set of bias currents considered is I0∈[50,100,150,200,250,300] μA. Table 1, Table 2, Table 3, Table 4, Table 5, Table 6 show the optimal design

Conclusion

In this work, we have successfully demonstrated how CMOS positive second generation Current Conveyors (CCII+) can be optimally designed for enhanced performance. The design is directed to simultaneously minimize the parasitic X-port input resistance (RX) and maximize the high end cut-off frequency of the current signal (fci). The problem is solved using bacterial foraging optimization (BFO) algorithm, a recently developed non-gradient type stochastic optimization algorithm. This algorithm

Acknowledgements

Amitava Chatterjee was with Laboratoire Images, Signaux et Systèmes Intelligents (LiSSi, EA 3956), Université Paris XII Val de Marne, 61 avenue du Général de Gaulle, 94010 Créteil, France, as an Enseignant Invité (Invited Teacher), when this work was performed. He was on leave from Electrical Engineering Department, Jadavpur University, Kolkata 700032, India.

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