Elsevier

Microelectronics Journal

Volume 45, Issue 11, November 2014, Pages 1522-1532
Microelectronics Journal

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

https://doi.org/10.1016/j.mejo.2014.08.012Get rights and content

Highlights

  • A reversible QCA multiplexer logic (RM) is designed from irreversible multiplexer.

  • Results show the effectiveness of the design in terms of cost and testing overhead.

  • Fault testing capability is reported.

  • A complete testable reversible arithmetic logic unit (RALU) is synthesized based on separate module of RAU and RLU.

  • Reliability issue is addressed with modularity.

Abstract

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability.

Introduction

Current digital design techniques target energy efficient realization of complex CMOS circuits. As conventional CMOS has its own physical limits, that hinder the reduction of energy loss in logic circuits, researchers have switched to the novel nanotechnology, the quantum-dot cellular automata (QCA) [1]. In QCA, Coulombic interaction provides necessary computing logic states of 1 and 0 by the position of the electrons inside the QCA cell. Thus, when the bit is changed from 1 to 0 there is no actual discharging of the capacitor as in conventional CMOS. Further, unlike conventional logic circuit in which information is transferred by electric current, QCA utilizes the Coulombic interaction of the electrons to propagate the polarization effect from one cell to other, i.e. there is no current flow. Hence, QCA does not have to dissipate all its energy during signal transition and propagation [2]. This has significant advantage than that of CMOS technology in terms of power dissipation. Further, the downscaling of CMOS circuitry does not necessarily produce corresponding gains in device density [3]. But the smaller dimension of QCA cells causes QCA interconnect to shrink, thereby increasing device density.

One of the prominent sources of energy dissipation in any nanotechnology is the loss of bits or information which significantly contributes to the overall heat dissipation of the system [4], [5]. The quantity of energy dissipated in a system bears a direct kinship to the number of bits erased during the computation. The energy required for binary transition Ebit is given by the Shannon–von-Neumann–Landauer (SNL) expression [6], EbitESNL=kBTln2=0.017 eV, where kB is the Boltzmann constant, T=300 K. This is the minimum energy required to process a bit. Whenever a physical system throws out information about its previous state it must engender a comparable measure of entropy. Landauer [7] proved that for irreversible logic computations, a single bit loss results in dissipation of kBTln2 joules of heat energy. Further, Bennett [8] demonstrates that the kBTln2 energy dissipation cannot happen if a computation is taken away in a reversible way. Reversibility in computing implies that no information about the computational states can ever be lost and any earlier stage can be recovered by computing backwards or uncounting the results. A reversible circuit is designed using the reversible gates that can generate a unique output vector from an input vector and vice versa. The classical logic gates are irreversible since an input vector state cannot be uniquely reconstructed from the output vector state. Moreover, the reversible logic operations do not erase (lose) information and dissipate very less energy.

An alternative approach to reduce the power dissipation in current digital technology is the use of adiabatic principles in logic circuits [7], [9]. The presence of quasi-adiabatic switching in QCA makes the QCA more energy effective [10]. The quasi-adiabaticity of the switching means that the system is very close to its ground state during the whole switching process. It does not reach an excited state after setting the new input, this is in contrary to the abrupt switching. Since the system is not allowed to get to an excited state from the ground state, the dissipation to the environment is minimal. So, there is a need for conceptual and technological changes so that both reversibility and adiabatic principles can be integrated in the currently available technology. Thus QCA based reversible logic is emerging as a lucrative option in the field of electronic circuit design.

Multiplexer based circuits [11] such as data transmission logic, FPGA, memory circuits are available in the literature citing its immense applicability in the field of digital electronics. But the effectiveness of multiplexers for synthesizing high level logic circuits in QCA has not been investigated till date. In this context, our proposed work explores the design of a reversible arithmetic and logic unit (RALU) in QCA technology. The major contributions of this work revolving around logic based QCA architecture can be summarized in the following points:

  • Design of a cost-effective 2:1 multiplexer using QCA followed by its cost effective approach toward least chip-area coverage.

  • Synthesis of a reversible structure of 2:1 multiplexer (RM) by the proposed compact 2:1 multiplexer.

  • Design of reversible logic unit (RLU) and arithmetic unit (RAU) using the proposed reversible multiplexer followed by synthesis of the reversible arithmetic and logic unit (RALU) with the increase in programmability. The proposed design of RALU is shown to be most efficient on the basis of function generation capability and speed of computation.

  • Development of the concurrent testing strategy for detection of any stuck-at fault using only two test vectors.

The rest of the paper is subdivided into the following sections. Section 2 defines the basics of QCA and reversible logic. In Section 3, a compact 2:1 multiplexer is introduced. Reversible multiplexer (RM) structure is synthesized in Section 4. In Section 5, reversible QCA multiplexer is applied in designing RALU followed by its capability in function generation. Testability of the proposed RALU is evaluated in Section 6. Necessary simulator settings for the experimentation are given in Section 7. A detailed discussion on the power consumption of proposed logic is reported in Section 8. Section 9 evaluates the paper.

Section snippets

Background

QCA cell consists of four quantum dots positioned at the corners of a square and contains two free electrons [1]. A quantum dot is a region where an electron is quantum-mechanically confined (Fig. 1(a)). The electrons can quantum-mechanically tunnel among the dots and settle either with cell polarization (arrangement of charge and not the dipole moment of cell) P=−1 (logic 0) or in P=+1 (logic 1) as shown in Fig. 1(b).

Design of cost effective QCA multiplexer

The output of a 2:1 multiplexer is given byOut=Sel.A+Sel.BA and B are the two data inputs and Sel is the select line. The majority gate representation of this multiplexer is shown in Eq. (2). That is, 3 majority gates and 1 inverter are needed to implement a 2:1 multiplexer (Fig. 6):F=M3(M1(Sel¯,A,0),M2(Sel,B,0),1)

Lemma 3.1

The minimum number of clock zones required to implement a 2×1 multiplexer using QCA majority primitives is two.

Proof

For a 2×1 multiplexer, the basic output function is given by f=Sel’.A +

Synthesis of reversible multiplexer (RM)

It is already established that embedding an irreversible calculation in a reversible circuit by echoing inputs to outputs does indeed result in a huge reduction of the power dissipated [10]. In this section, a reversible multiplexer is synthesized using the irreversible multiplexer introduced in the earlier section. Fig. 8 shows the reversible multiplexer (RM) structure realized using 2:1 multiplexers. The input to output mapping of RM is P=A⊕BC, Q=A׳B + AC, R=A׳C + AB, where A, B, C are the

Reversible ALU (RALU)

The arithmetic logic unit (ALU) is an important constituent of the CPU, as it performs most of the arithmetic and logical operations. It has become an utmost necessity for an effective reversible circuit to increase the depth of programmability of the logic device, i.e. the number of logical calculations produced on the fixed outputs. Also, for a flexible ALU, any modification for implementation in an instruction set architecture should be simple. All of the above factors suggest a modular

Testability of ALU

The normal functioning of the reversible logic unit is described in the earlier section. Individual performance of the RAU and the RLU block is also provided. However, for the purpose of testing, truth tables corresponding to the primary inputs A and B are made, and the third column (fault free output) of Table 7 gives the values of the primary output based on the control values. Considering the control values to be fault free, we have tested for stuck-at faults for inputs A, B and the primary

Simulation setup

All the designs are verified using QCADesigner version 2.0.3 [25]. In the bistable approximation, we have used the following parameters: cell size=18 nm, number of samples=182,800, convergence tolerance=0.001000, radius of effect=41 nm, relative permittivity=12.9, clock high=9.8× e22, clock low=3.8× e23, clock amplitude factor=2.000, temperature=1 K, layer separation=11.5000 nm, and maximum iterations per sample=1000.

Discussion

The current design targets logical reversibility in QCA framework. The importance of logical reversibility is established in [5], [10], [8]. In [4], it is established that power effective circuits can be designed with varying levels of logical reversibility independent of physical reversibility. To realize a reversible circuit using the Landauer clocking, the component logic gates must also be reversible. However, an information preserving approach is developed in [18] based on logical

Conclusion

This work proposes a modular reversible arithmetic logic unit (RALU) which consists of two separate modules – reversible logic (RLU) and reversible arithmetic unit (RAU). Both the RLU and the RAU are synthesized based on reversible multiplexer (RM) logic introduced in this work having 59% inherent fault tolerance capability in QCA technology. The 100% fault tolerance capability against single missing and additional cell deposition in QCA can be attained by using a fault tolerant structure for

Acknowledgments

We would like to express our sincere thanks to the anonymous reviewers for their critical suggestions which helped in improving the paper.

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