Elsevier

Microelectronics Journal

Volume 54, August 2016, Pages 150-165
Microelectronics Journal

Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin

https://doi.org/10.1016/j.mejo.2016.05.009Get rights and content

Highlights

  • Two-stage subthreshold bulk-driven, gain, GBW, phase-margin enhanced OTA1 is proposed.

  • OTA2 adds class AB buffer having negative feedback via two-CMOS transmission gates.

  • OTA2 drives R-C shunt load and these OTAs are employed to realize active R-C filters.

Abstract

This paper presents sub-threshold, bulk-driven two-stage cascode compensated operational transconductor, which drive load up to 60 pF. The input core in the first stage uses a bulk-driven source-degenerated, gate-regenerated class AB flipped voltage follower (FVF), which ensures rail-to-rail linear input signal drive capability in its unity gain configuration. The self-cascode load of input stage followed by a common source (CS) second stage having simple current source load, have enhanced overall gain around 100 dB at 1 mHz. Instead of Miller compensation, cascode compensation has been implemented by using two capacitors (CC/2) each of value 4 pF in this OTA. It has increased its phase margin and gain bandwidth as compared to Miller compensation, under identical load and total compensation capacitors. It ensured better rail-to-rail linearity (THD <−44 dB) at 200 Hz frequency consuming around 74 nW power from ±250 mV dual power supply.

Another three-stage OTA is also proposed, which includes one additional CS class AB buffer at the output of OTA1, to drive R–C shunt load. This buffered OTA is additionally nested Miller compensated using capacitor (CNMC) of 0.2 pF. This buffering enhances slew rate and gain bandwidth (GBW) by two-times as compared to un-buffered structure at the cost of power.

The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuits.

Introduction

The OTA is an important analog building block, generally used in open as well as closed loop configurations in Gm-C analog filters. A large time constant in low-frequency applications require very large capacitors and passive resistors in RC filters. The very large resistor can be realized using OTA, which requires small chip area as compared to diffusion technology based polysilicon resistors. OTA are used in the input core of op-amps and current conveyors, so it should provide sufficient open loop gain to ensure the closed loop transfer function independent of the overall forward path gain of the OTA/op-amp, when used in negative feedback loop. It also requires high common mode rejection ratio (CMRR), high power supply rejection ratio (PSRR), reasonable slew rates and rail-to-rail input as well as output signal dynamic range for low-voltage (LV) and low-power (LP) battery operated appliances such as calculators, bio-instruments, human implants, pacemakers, ear phone, head phone, cell phones, etc.

The design of mixed signal SoC chip in deep-submicron CMOS technology prefer the analog circuits to be driven by the available on chip supply to avoid the need of on-chip charge pump boosted supply, which is noisy for both digital and analog circuits. The gate driven analog circuits requires minimum rail-to-rail power supplyVDD+|VSS|=2[VTH+2VOV], where VTH is threshold voltage of MOSFET and VOV is over drive voltage. Thus at least 1.8 V supply is required to ensure 0.9 V across series stack of MOSFETs in input stage to keep them in saturation and remaining 0.9 V for output signal swing in 180 nm CMOS process. So the gate-driven topology is not a suitable choice for low-voltage (0.5 V) circuits. Novel innovative analog design techniques need to be employed to get reasonable performance under such LV environment. The device level approach needs complex and costly additional fabrication steps, so it is less preferred over circuit level approach [1], [2]. In the latter approach, first of all, the compliance voltage (0.25 V) across MOST's and secondly its threshold voltage (nominally 0.5 V) should be minimized to ensure reasonable output signal swing. However the VTH do not follow constant electric field scaling and lags behind voltage scaling. Due to this threshold voltage hurdle the low-voltage OTA utilize bulk-driven (BD) approach, which avoids the need of threshold voltage from the signal path and can work satisfactorily using rail-to-rail supply of one threshold voltage (around 0.5 V) [3], [4], [5].

The bulk-driven transconductance (gmb) is η (0.2–0.4) times smaller than gate-transconductance (gm), where η is called body effect transconductance ratio. It also reduces GBW to 1/10 times and basically suits for low-frequency applications, owing to higher input capacitance involved at bulk input terminal [6], [7]. G. raikos, S. Vlassis have implemented 100% positive feedback at gate terminals of bulk-driven input pair to enhance its transconductance [6]. Many other authors have suggested partial positive feedback to enhance the transconductance and GBW for bulk-driven pair [7], [8], [9], [10], [11], [12], [13], [14], [15], [16] and this partial-regeneration increases the current drive capability of low bias current (<150 nA) based sub-threshold circuits. Though the BD-MOST approach overcomes the need of VTH (0.5 V), yet it requires MOST compliance voltage equal to that of gate-driven circuits. The sub-threshold region operation need around 78 mV across the devices whereas strong inversion needs VOV >200 mV, hence sub-threshold operation favors LV design [13]. So to design a high open loop gain and rail-to-rail linear OTA a source-degenerated, bulk-driven PMOS input core has been preferred in reported works [17], [18], [19], [20], [21], [22]. The PMOS input core structure provides reduced flicker noise as compared to NMOS based design. In addition to this the PMOS input design trends favors standard single n-tub CMOS technology, in which the PMOSTs can be fabricated in isolated bulk, avoiding the need of complex and costly twin-tub CMOS process technology [10], [11].

The OTA having cascaded stages require frequency compensation to ensure reasonable phase margin and stability. A high gain around 100 dB further reduces the phase margin and realization of Miller compensation and its nulling resistor (MOS based) is difficult to design in such a LV environment. It requires high value CC, which reduces slew rates and GBW and dissipates more power during charge discharge transients [23], [24]. The pseudo cascode compensation as well as conventional cascode compensation has been reported in [25] to enhance the phase-margin and GBW of two-stage LV op-amps operating in strong inversion. However the OTA reported in [26] has utilized pseudo cascode compensation for its gate-driven MOSFETs, biased in weak inversion region.

In this paper a two-stage single ended output bulk-driven OTA (called OTA1) operating in sub-threshold region has been proposed. The first stage is comprised of an input core as in [17], [22] followed by self-cascode current mirror load based CS amplifier. The second stage uses a simple MOS current source load in its CS configuration to ensure maximum output signal swing. This two-stage OTA is cascode compensated by using two split compensation capacitors CC/2 rather a single Miller capacitor (CC). This compensation has ensured reasonable phase margin for widespread load capacitor [26].

This OTA is further modified by including a buffer stage comprised of class AB push-pull, CS inverter. It utilizes negative resistive feedback to reduce its output impedance to drive shunt combination of high capacitive load (up to 100 pF) and low resistive load down to10 kΩ satisfactorily [20]. The loading with additional shunt load of 10 kΩ reduces the voltage gain but it remains well above 60 dB. This resistive feedback has been successfully replaced by active CMOS transmission gates to make this buffer suitable for SoC fabrication. This three-stage buffered OTA is addressed as OTA2 throughout the text.

The remaining paper is organized in the following five sections. Section 2 describes the OTA1 and OTA2 circuit, Section 3 states some of the performance equations, and Section 4 presents pre-layout and some post-layout simulation results and process, voltage and temperature (PVT) variation effects on their performances. The Section 5 highlights on their applications as low-frequency active R–C filters and comparison of their performances to some of the reported works and Section 6 concludes the various results.

Section snippets

Proposed two-stage OTA

Fig. 1 shows the circuit schematic of the proposed OTA1. The input core (dashed area) consists of PMOS input pair (P1, P2) with flipped voltage follower pair (P3, P4) [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], source-degeneration resistor (2RS) and diode connected load NMOS pair (N1, N2). This input pair also includes a gate-regenerative feedback loop to enhance its transconductance [6], [22]. The PMOS input core having bulk-driven differential pair is utilized to favor

Performance equations

The device sizing in weak inversion [27], [28] is governed by inversion coefficient (IC), which is related to shape factor S given byS=ISD/ICISwhere the value of IS in 0.18 µm CMOS process is around 0.64 µA, which demands a minimum S of 2 at a bias current of 11.6 nA and IC of 0.01 [26]. In this design the S of NMOS and PMOS are selected to be 2 and 25, respectively, which confirms their weak inversion operation. The PMOS input pair lies in isolated tub and encounter body bias effect causing

Simulation results

The proposed OTAs have been simulated in cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology at 300 K temperature. The MOSFETs (except cascode transistors in each SC pair, which are in zero region) are biased in weak inversion. The input core generates a DC bias current of 23.3 nA when biased by dual supply of (± 0.3 V), whereas this input current is reduced to 5.45 nA at dual power supply of (±0.2.5 V). The dual supply biasing has been used to set common mode voltage to 0 V. The

Application in gm-C filters

The OTAs having high impedance at output as well as input nodes are suitable to derive gm-C filter functions. The proposed OTA have high impedance at multiple output nodes so they are suitable to realize active RC filters rather a gm-C. The RC filter can be used for low-frequency signal processing and its cut-off frequency depends upon R and C components. These R–C network may be either off-chip or on-chip components. They can also realize switched capacitor filter functions. The proposed

Conclusions

In this work two sub-threshold region operated OTAs have been proposed. The OTA1 and OTA2 are able to drive load capacitor up to 60 pF and 40 pF, respectively with two cascode compensation capacitors each of 4 pF. The proposed OTA1 provided 99.5 dB open loop gain and 6.2 kHz gain bandwidth with good linearity having THD of − 44 dB at rail-to-rail input signal swings at 200 Hz in its unity gain configuration consuming 74-nW power. The five-fold increase in GBW has been observed if power supply is

Conflict of interests

The authors declare that there is not any conflict of interests regarding the publication of this paper.

Acknowledgment

This work has been performed using the resources of VLSI laboratory developed under Special Manpower Development Program for VLSI design and related software (SMDP-II) project funded by Department of Information Technology, Ministry of Communication and Information Technology, Government of India at MNNIT Allahabad, UP. However, the revision work has been performed in Cadence Spectre UMC 0.18 μm CMOS process technology available in VLSI laboratories of ECE and EE departments of NERIST deemed

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