A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA

https://doi.org/10.1016/j.micpro.2012.06.012Get rights and content

Abstract

A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF.

Introduction

Field Programmable Gate Arrays (FPGAs) offer an economical and rapid solution for medium to low volume production of digital circuits. This is mainly because of the generalized nature of their reconfigurable resources that can be programmed in a short time to implement any kind of digital circuit. These advantages, however, come with some significant disadvantages. Compared with non programmable devices (e.g. Application Specific Integrated Circuits (ASICs)), FPGAs have larger area, poor performance and higher power consumption. Authors in [1] have reported that FPGAs are 20–35 times larger, 3–4 times slower and 7–14 times more power consuming than ASICs. This area, performance and power gap limits the applicability of FPGAs when either of these parameters are not met for a certain application. To address this limitation, a number of alternatives to FPGAs exist.

The primary alternative to an FPGA is an ASIC that has speed, power and area advantages over an FPGA. However, ASIC design requires huge resources in terms of time and money and has become increasingly complicated with advancement in process technology. The difficulties associated with the design process of ASICs have led to the development of Structured-ASICs. Structured-ASICs can cut the NRE cost of ASICs by more than 90% while speeding up significantly their time to market [2]. Structured-ASICs are explored or manufactured by several companies [3], [4], [5], [2]. FPGA vendors have also started giving provision to migrate FPGA based application to Structured ASIC. In this regard, Altera has proposed a clean migration methodology [6] that ensures equivalence verification between FPGA and its Structured-ASIC (known as HardCopy [7]). However, migration of an FPGA based application to HardCopy can execute only a single circuit and it totally loses the quality of reconfigurability. An ASIF, on the other hand, comprises of optimized logic and routing resources like Structured-ASIC but retains enough flexibility to implement a set of predetermined applications that operate at mutually exclusive times. Fig. 1 presents the ASIF generation concept. In the final phase of development cycle of an FPGA based product, if the set of circuits to be mapped on the FPGA are known, it can be reduced to an ASIF for all the given set of circuits. Execution of different application circuits on ASIF can be switched by loading their respective bitstream on ASIF.

The concept of an ASIF is similar to configurable ASIC cores, abbreviated as cASIC [8]. cASIC is a reconfigurable device that can implement a predetermined set of circuits that operate at mutually exclusive times. However, there are several basic differences between cASIC and ASIF. cASIC is mainly used as an accelerator in a domain-specific systems on chip, and it supports only full-word logic blocks (such as 16-bit wide multipliers, adders, and RAMs) to implement data-path circuits. However, an ASIF supports both soft-blocks and hard-blocks and it can be used to implement an entire design. Similarly, cASIC uses segmented bus-based routing where signals are routed in 16-bit wide buses whereas ASIF uses fine-grain routing where signals are routed in a bit by bit manner.

Generation of an ASIF from an FPGA makes its architecture irregular; hence making its layout more difficult as compared to FPGA. Although the effort required for the layout of ASIF is comparatively less than that of ASIC, it will occupy more area than ASIC. Also commercial synthesis tools can be used to generate a standard cell based ASIC that can execute multiple application circuits at mutually exclusive times. However, contrary to ASIF, commercial tools are unable to exploit the resources shared by the circuits [8]. Also, unlike an ASIF, an automatically generated ASIC is less probable to repeatedly use hardware components like LUTs; hence full custom layout of repeatedly used cells is not viable for ASICs.

In this work we present new heterogeneous tree-based ASIF. A preliminary version of this work was initially presented in [9]. However, here we perform a detailed exploration of different ASIF generation techniques for tree-based ASIF that were not initially presented and also we perform a comparison between ASIF and equivalent tree-based FPGA. Further, we present a profound and detailed analysis of the results already presented in [9] and finally we present a new automatic ASIF hardware generator.

The remainder of the paper is organized as follows: Section 2 gives a brief overview of heterogeneous mesh and tree-based FPGA architecture that are used in this work. Section 3 describes their associated software flow which is used to efficiently place and route benchmarks on both architectures. Later these FPGA architectures are reduced to their respective ASIFs. Section 4 details different ASIF generation techniques and Section 5 describes the area model used to calculate the area of ASIF. Section 6 presents experimental results, Section 7 details the ASIF hardware generation and Section 8 finally concludes this paper and presents some future work.

Section snippets

Reference heterogeneous FPGA architectures

This section gives a brief overview of heterogeneous mesh-based and tree-based FPGA architectures. Application circuits are efficiently placed and routed on these architectures and later they are reduced to their respective ASIFs. Both mesh and tree-based FPGA architectures comprise of similar logic and routing resources. However, it is the arrangement of these logic and routing resources that separates two architectures. In mesh-based FPGA architecture logic and routing resources are arranged

Software flow

Since we are considering two architectures in this work, an effort is required to ensure transparency for comparison between them. For this purpose, we have designed separate software flows that efficiently place and route different benchmarks on two architectures. Some parts of software flow are shared while rest of them are designed specifically to meet the needs of two architectures. A detailed overview of different steps involved in the software flow is as follows.

ASIF generation techniques

Reconfigurability of FPGAs is their biggest asset but at the same time it is also their largest drawback as it makes them larger, slower and more power consuming than ASICs. Customized reconfigurable architectures like ASIF can reduce these overheads of FPGA while maintaining a certain degree of flexibility. An ASIF is reduced from an FPGA where a set of predetermined applications are placed and routed and later all unused reconfigurability is removed to generate ASIF. In order to generate an

ASIF area model

A generic area model is used to calculate the area of ASIF and this model is applicable to both mesh and tree-based ASIFs. The area model of mesh and tree-based ASIFs is based on respective FPGA architectures where netlists are efficiently placed and routed on them and later unused resources are removed to generate ASIF. As mentioned in [27], discussions with FPGA vendors have revealed that transistor area, and not wiring density, is the area limiting factor. The use of directional wires in

Experimentation and analysis

ASIF generation techniques explained in Section 4 are explored for tree-based architecture. Tree-based ASIFs are generated for two sets of benchmarks. Details regarding the conversion of these benchmarks (netlists) from HDL format to NET format are already described in Section 3 where netlists with different LUT sizes can be generated using the software flow of Fig. 5. Details of netlists for two sets with LUT size 3 and 7 are shown in last two columns of Table 1, Table 2 respectively.

This

ASIF hardware generation

A new automatic ASIF hardware generator is presented in this work that generates the VHDL model of ASIF. This model is later passed to Cadence Encounter to generate the layout using 130 nm 6-metal layer CMOS process technology of ST Microelectronics. Main steps involved in the hardware generation of ASIF are as follows:

Conclusion and future work

In this work, a new heterogeneous tree-based ASIF is presented. An ASIF is a modified form of FPGA that has reduced flexibility and improved density. It is basically an attempt to explore the design space between FPGA and ASIC. An ASIF can be viewed as configurable ASIC or a less flexible FPGA; bringing together the advantages and disadvantages of both together. In this work we have explored different ASIF generation techniques using a total of 17 open core benchmarks. Based on the types of

Umer Farooq received his bachelors in electronics from University of Engineering and Technology Lahore Pakistan in 2004, and his masters degree in embedded systems from university of nice Sophia antipolis, France. Currenlty he is an assistant Professor at CIIT, Lahore.

References (30)

  • I. Kuon et al.

    Measuring the gap between FPGAs and ASICs

    IEEE Transactions on Computer Aided Design

    (2007)
  • K. Wu et al.

    Structured ASIC, evolution or revolution

    International Symposium on Physical Design

    (2004)
  • T. Okamoto et al.

    Design methodology and tools for NEC electronics structured ASIC

    International Symposium on Physical Design

    (2004)
  • D. Sherlekar

    Design considerations for regular fabrics

    International Symposium on Physical Design

    (2004)
  • eASIC, 2010....
  • J. Pistorius et al.

    Equivalence verification of FPGA and structured ASIC implementations

    International Conference on Field Programmable Logic

    (2007)
  • HardCopy, HardCopy IV ASICs, Device Handbook,...
  • K. Compton et al.

    Automatic design of area-efficient configurable ASIC cores

    IEEE Transaction on Computers

    (2007)
  • U. Farooq et al.

    Comparison between heterogeneous mesh-based and tree-based application specific FPGA

    International Workshop on Applied Reconfigurable Computing

    (2011)
  • J. Luu et al.

    VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

    International Symposium on Field Programmable Gate Arrays

    (2009)
  • G. Lemieux et al.

    Directional and single-driver wires in FPGA interconnect

    International Conference on Field Programmable Technology

    (2004)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez, A new Tree-Based Coarse-Grained FPGA Architecture, International...
  • B. Landman et al.

    On pin versus block relationship for partition of logic circuits

    IEEE Transactions on Computers

    (1971)
  • U. of Toronto FPGA Research Group, 2010....
  • O. Cores, 2010....
  • Cited by (10)

    • Prototyping using multi-FPGA platform: A novel and complete flow

      2023, Microprocessors and Microsystems
      Citation Excerpt :

      But the main drawback of these benchmarks is that they are quite small in size and homogeneous in nature. Researchers in [30] have used a total of twenty heterogeneous benchmarks in their exploration flow for heterogeneous FPGAs. These benchmarks are quite complex and have moderate complexity.

    • Novel architectural space exploration environment for multi-FPGA based prototyping systems

      2018, Microprocessors and Microsystems
      Citation Excerpt :

      For example, authors in [22] present a set of twenty homogeneous benchmarks that have long been used by research community. Furthermore, authors in [23] use two sets of heterogeneous benchmarks which are used for exploration of heterogeneous FPGA architectures. But the benchmarks used in both aforecited works are simple and they are too small to challenge the capability of multi-FPGA prototyping tools.

    • Exploring FPGA Logic Block Architecture for Reduced Configuration Memory

      2022, Advances in Electrical and Computer Engineering
    • Pre-Silicon Verification Using Multi-FPGA Platforms: A Review

      2021, Journal of Electronic Testing: Theory and Applications (JETTA)
    View all citing articles on Scopus

    Umer Farooq received his bachelors in electronics from University of Engineering and Technology Lahore Pakistan in 2004, and his masters degree in embedded systems from university of nice Sophia antipolis, France. Currenlty he is an assistant Professor at CIIT, Lahore.

    Husain Parvez received his Bachelors of Engineering degree in Computer Science from National University of Sciences and Technology, Islamabad, Pakistan in 2002, masters and PhD in Computer Science from UPMC, Paris, France in 2006 and 2010 respectively. Currenlty he is an assistant professor at PAF KIET, Karachi.

    Habib Mehrez received bachelors degree in electronics from Tunis in 1979, masters in electronics from University of Orsay, France in 1983, and PhD from UPMC, France in 1991. Currently, he is the head of the team CIAN at SoC department of LIP6, France.

    Zied Marrakchi completed bachelors in electronics in 2002 from Tunis electrical engineering school, masters from Suppelec, Rennes, France in 2005 and PhD from UPMC, Paris, France in 2008. Since then he is working at Flexras Technologies, a start-up company, which he co founded with a fellow PhD student.

    This document is a collaborative effort.

    View full text