A FPGA based implementation of Sobel edge detection
Introduction
Edges are basically the noticeable variation of intensities in an image. Edges help to identify the location of an object and the boundary of a particular entity in the image. It also helps in feature extraction and pattern recognition. Hence, edge detection is of great importance in computer vision. So far, most of the researchers have chosen software for implementation of basic edge detection algorithms and their variations [2]. But, it has been established that it is not an efficient approach for real time applications. Implementation of edge detection algorithms on hardware platform is more efficient for real time applications. With the advancement of VLSI technology, hardware implementation presents a scope to parallelize subroutines in a program. Hence, hardware implementation provides much faster alternative as compared to software. In 1994 Boo et al. [3] have proposed hardware implementation of edge detection using Sobel operator using VLSI technology within application specific integrated circuit (IC). In the past few years extensive work has been done in the area of Field programmable Gate Array (FPGA) based implementation of edge detection algorithm which in turn implements image processing in real time. In 2009 real time algorithms have been designed to detect edges on FPGA board [12]. Parallelism of any algorithm is possible due to integration of large number of transistors (10k–100k) on a single silicon chip using VLSI technology [10]. All embedded systems are designed and implemented on Application Specific Integrated Circuit (ASIC) or FPGA. FPGA is an IC with Configurable Logical Blocks (CLBs) [5]. CLBs are interconnected using routing channels on a silicon board based on the desired operation. The internal connections can be configured using Hardware Description Languages (HDL) like VHDL [9] or Verilog. The silicon board consists of input/output ports on the boundary to take the input and provide the output as shown in Fig. 1. These HDLs provide a medium of simulation of the designed IC to see if anything can go wrong. These programmed ICs are emulated on FPGA board after correct simulation. In 2007, Abbasi et al. [1] presented an architecture for Sobel edge detection on FPGA. Later in 2012, this architecture was found to be inefficient with respect to space and time complexity by Halder et al. [8]. Architecture proposed by them saved time and took lesser space than the architecture proposed by Abbasi et al. [1]. However, this architecture also had disadvantages of redundant storage of pixels and also there is scope of reduction in the architecture. The motivation of proposed work is to overcome these shortcomings of architecture proposed in [8]. The contributions of the present work are as follows:
- •
An 8-bit architecture has been proposed to retrieve the addresses of pixels involved in convolution process for reducing the space complexity in the convolution process.
- •
A modified architecture by replacing some components in the architecture proposed by Halder et al. [8] for reducing the time complexity of Sobel edge detection algorithm.
The organization of the paper is as follows. Section 2 gives a brief introduction of Sobel edge detection algorithm. Section 3 presents a modified version of the traditional Sobel edge detection algorithm. Section 4 depicts the methodology followed in this work. Experimental results and discussion are presented in Section 5. Finally, Section 6 concludes this work.
Section snippets
Sobel edge detection algorithm
Sobel edge detection algorithm is a gradient based edge detection method [6], [7], which finds edges using horizontal mask (HM) and vertical mask (VM) [11]. One mask is simply transpose of the other as follows:For the convolution process, an image is scanned from left to right and top to bottom of an image using HM and VM separately. Convolution is the process multiplying each intensity value of an image with its local neighbors, weighted by the mask. Let [P]
Simplification of the traditional Sobel edge detection algorithm
A few adjustments are required in traditional Sobel edge detection algorithm because 8-bit architecture has been adopted here for hardware implementation. In [8], Halder et al. simplified the traditional algorithm. Some changes have been done in the simplified version of algorithm proposed by Halder et al. [8]. In Eq. (1), the values of f1 and f2 will be maximum when each of the contributing pixels of sub-window will have maximum intensity values, i.e., 255. The same happens with f3 and f4 in
Methodology
Let image I is stored as a rectangular array of elements, ‘A’ with m rows and n columns. As memory of the computer is simply a sequence of addressed locations, the programming language stores this two-dimensional array, ‘A’, in memory by a block of m × n sequential memory locations either row by row in row-major order or column by column in column-major order. The order of elements and their adresses change with the above specified techniques. This can further be illustrated with an example.
Experimental results and discussion
The proposed architectures are implemented using VHDL. The program is simulated followed by synthesis on Xilinx Sparta 6 XC6SLX43TQG144 FPGA board. The simulation is done on grayscale images of various sizes using a predefined threshold. Fig. 12 shows 8-bit grayscale input images and their corresponding edge images by hardware and software implementations respectively. In both the cases, same threshold of intensity value 27 has been chosen.
Table 1 shows the comparitive study of device
Conclusions
The proposed architecture of Sobel edge detection uses direct indexing of desired pixels unlike the redundant storage of sub-window pixels as in the previous architectures thus reducing space complexity. The circuit is able to perform at a faster frequency than existing designs. Hence, the time to process an image is less comparatively. When this architecture is used for large databases it will show a significant difference. The time complexity of the proposed algorithm is less than previously
Acknowledgments
Ayan Seal is thankful to Deity, Government of India for providing him Young Faculty Research Fellowship under Visvesvaraya PhD Scheme for Electronics and IT.
References (12)
- et al.
A real-time edge detector: algorithm and vlsi architecture
Real-Time Imaging
(1997) - et al.
A proposed fpga based architecture for sobel edge detection operator
J. Act. Passive Electron. Devices
(2007) - et al.
Vlsi implementation of an edge detector based on sobel operator
EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.
(1994) - et al.
Architecture of fpgas and cplds: a tutorial
IEEE Des. Test Comput.
(1996) - et al.
Field-Programmable Gate Arrays
(2012) - et al.
Pattern Classification and Scene Analysis
(1973)
Cited by (84)
“Terrace compression method” and its application in heterogeneity contour detection of transmission images
2022, Optics CommunicationsCitation Excerpt :The contour, as the key feature information of an image, is the basis for analyzing or understanding the target object. Traditional contour detection is performed by convolving images with local filters to capture discontinuous features of gray intensity for detection [12], such as the Sobel [13], the Robert [14] and the Prewitt [15] operators. These operators are usually sensitive to noise and work reasonably well for simple and common edge detection, but they are far from satisfying in contour detection tasks.
A knowledge augmented deep learning method for vision-based yarn contour detection
2022, Journal of Manufacturing SystemsMonitoring coastline variations in the Pearl River Estuary from 1978 to 2018 by integrating Canny edge detection and Otsu methods using long time series Landsat dataset
2022, CatenaCitation Excerpt :The Otsu method is an algorithm proposed by Otsu (1979) to separate water from land using a threshold selection method from gray-level histograms and was considered the most classic threshold segmentation method. The basic idea of this method is to select a suitable threshold and then use the maximum value between-cluster variances to separate the background and aimed object (Nazma et al., 2018). Edge detection is recognized as a tool to extract the boundary of a particular image (Chen et al., 2019; Zhang et al., 2013).
Low resource FPGA implementation based efficient image edge detector architecture
2024, Multimedia Tools and Applications