A new built-in screening methodology to achieve zero defects in the automotive environment

Abstract

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring.

Introduction

The ability to control the random defectivity of a product during its life cycle becomes more and more vital especially in the automotive field, where the drive towards “zero defects” is very stringent.

In particular, gate oxide defects and crystal defects are a major constraint in the development of reliable devices because of the extensive use of large gate and junctions areas for power applications.

According to the usual defective oxide classification, Class A includes such oxides, which are expected to fail (usually due to pinholes) for an applied field strength (E_BD) lower than 1 MV/cm. Class B includes the so-called extrinsic oxides that fail for an E_BD lower than the intrinsic value, and Class C includes those oxides, which fail at an E_BD above 10 MV/cm (for the thickness range of interest in this paper) due to intrinsic dielectric breakdown. At present the required failure rate during the life cycle of the product is assured by properly designed screening procedures before and after packaging of the chip, which force oxides in the Class A and B to fail, without introducing any substantial pre-damaging of the robust subpopulation [1].

Crystal defects (e.g. dislocations and stacking faults) can be either inherently present in the bulk silicon, or generated during some critical process steps like epitaxial growth, implantation, and the formation of shallow trench isolations. During the lifetime of a device, crystal defects can coalesce or act as a gettering site for dopant atoms and contaminations. This can result into the formation of local highly conductive paths, which under some circumstances can heavily affect the performance of the integrated circuit [2], [3].

Nowadays, the most common procedure to screen gate oxide defects at chip level is still the so-called gate stress test (GST), where a high voltage pulse is applied through an automatic test equipment (ATE) to dedicated test pads of the LDMOS gate. Subsequently, the eventual occurrence of the oxide breakdown is detected by the measurement of the leakage current through the gate oxide.

The correlation between the presence of crystal defects and the increase of the transistor leakage current by various orders of magnitude is reported in the literature [2], [3]. For this reason, screening for crystal defects is usually accomplished by measuring the drain leakage current when the device is biased under subthreshold conditions after applying a high voltage pulse to the drain terminal. This procedure is usually defined as drain leakage test (DLT).

The main limitations of these traditional approaches are well-known. On one side they need expensive ATE, they require dedicated contact pads and overhead circuitry inside and outside the chip, they have very limited parallelization capabilities and finally they could be impossible after device packaging. On the other side, burn-in requires expensive equipment (load boards, control electronic, and thermal chambers), needs long testing times due to the limited acceleration factor, has limited accessibility to the points of interest, has to be carried out on finished devices and finally it still requires expensive parametric and functional tests that often exhibit a limited testing coverage. In addition, the numerous manipulations of the devices increase the risk of pre-damaging due to electrostatic discharges.

In order to solve these limitations, a new approach to the screening of defective gate oxides and junctions of LDMOS is presented, which is based on dedicated embedded circuitry to perform on chip the voltage stress and the measurement of the leakage current through the stressed device. Due to the fact that it relies on built-in circuit, the proposed solution can be applied both at chip level and to packaged devices, targeting directly the point of interest. Furthermore, since the whole process is managed by an internal circuitry, it does not require any additional testing equipment and can be run in parallel on a very large number of devices.

In this paper, the traditional GST and DLT approach in use nowadays for several automotive products are presented in Section 2, to point out requirements and limitations. In Section 3.1, the concept behind the novel built-in GST and DLT is defined together with its main constituting blocks. Section 3.2 describes in very detail the circuit solution used. In Section 3.3 the circuit layout and the results of the validation of the proposed design by transient SPICE simulations are proposed.