Single and dual gate OTFT based robust organic digital design

https://doi.org/10.1016/j.microrel.2013.09.015Get rights and content

Highlights

  • Performance analysis and comparison of single gate (SG) and dual gate (DG) OTFTs based inverters.

  • Observed that mobility of DG OTFT is almost five times higher than the SG.

  • Improved gain and noise margins of both DLL and ZVLL configurations using DG OTFT.

  • Using DG OTFTs, the propagation delay reduced by 59% for DLL and 42% for ZVLL in comparison to SG.

  • Bootstrap and back gate bias technique further enhanced the noise margin and gain.

Abstract

This paper analyzes and compares the performance of the single gate (SG) and dual gate (DG) organic thin film transistors (OTFTs) based inverter circuits. The DG-OTFT device performs better than SG-OTFT mainly in terms of mobility, on–off current ratio and sub-threshold slope. The mobility of DG device is almost five times higher than the SG, while, an increase of 74% in on–off current ratio and a decrease of 41% in sub-threshold slope are observed. Two different configurations of inverter circuits i.e. diode-load logic (DLL) and zero-Vgs-load logic (ZVLL) are studied. The static and dynamic behaviors of the p-type DLL and ZVLL inverters using SG and DG organic transistors are observed. The DG-OTFT improves gain and noise margins for both DLL and ZVLL inverter circuits. Using DG device, propagation delay reduces by 59% for DLL and 42% for ZVLL as compared to SG OTFT based configurations. Moreover, fixed back gate bias technique further enhances the noise margin and gain by 8% and 18% for DLL and 19% and 26% for ZVLL configurations, respectively. Finally, bootstrapping technique is also applied to the dual gate inverters that further boosts the noise margin and gain for DLL and ZVLL configurations.

Introduction

In last decade, the research in organic thin film transistor (OTFT) has undergone remarkable improvements. The key benefits of organic transistors are direct fabrication on flexible low-cost substrates and low processing temperatures that enables the cost efficient production. On consistent development, its integration in various applications is being pursued aggressively. OTFTs have been implemented as switching element for flexible display, organic light emitting diode [1], organic FET SRAM [2], RFID system [3], and sensors on plastic foils [4]. Currently, researchers targets to make use of this technology for circuits such as A/D converter [5], differential amplifier and ring-oscillator [6]. In spite of recent developments, still there is enough scope to achieve higher speed, larger current and lower power consumption by using novel device structures and materials.

Most organic inverter circuits make use of p-type designs only, due to lower mobility and instability of their n-type counterparts [7]. The n-type transistors are more sensitive to oxygen, air and moisture than p-types. Within available p-type materials, pentacene is the material of choice. The inverter circuits implemented in this work under different configurations are based on only p-type devices so as to achieve better performance. The static and dynamic behaviors of organic inverters in diode-load logic (DLL) and zero-Vgs-load logic (ZVLL) configurations are analyzed using single gate (SG) and dual gate (DG) organic transistors. It is observed that DG based inverters under different configurations outperforms the SG ones. Fixed back gate biasing and bootstrapping techniques are also used to further enhance the performance. Encouragingly, results show that the overall noise margin, speed and gain are further improved using these techniques.

This paper is arranged in five sections, including the current introductory section 1. Thereafter, section 2 analyzes pentacene based SG and DG devices, while in section 3, static and dynamic behavior of p-type organic inverter circuits in DLL and ZVLL configurations are dealt in. Section 4 analyzes the performance of DG device based inverters in DLL and ZVLL configurations using back gate biasing and bootstrapping techniques. Finally, section 5 summarizes the important outcomes of the proposed work.

Section snippets

Single and dual gate device analysis

A single gate TFT consists of a thin film of OSC, usually fabricated as the inverted structure with a gate (G) at the bottom. SG TFT can be categorized as top and bottom contact by means of relative position of source (S) and drain (D) contacts with respect to the semiconductor layer. In the top contact device structure, S/D electrodes are deposited on the semiconductor film, while in bottom contact devices; this deposition sequence is reversed [8] as shown in Fig. 1(a). Bottom contact devices

Organic inverter circuits

This section investigates the performance of organic p-type inverter circuit in DLL and ZVLL configurations, including single and dual gate transistors as shown in Fig. 6(a−d). These configurations are simulated under mix-mode, wherein, each input file is split into two parts; one describes the circuit net-list, and the other explains device simulation and model parameters [31]. It incorporates advanced numerical algorithm that effectively analyzes DC, transient, small signal AC and small

Improvement in performance of organic dual gate inverters

Noise margin is a figure of merit that accounts for the robustness and can be defined as the maximum tolerable noisy signal by a gate while showing correct operation [19]. Threshold voltage strongly affects the noise margin of an organic inverter [34]. Since, organic transistors are not intentionally doped, therefore, on a single substrate; generally, the transistors exhibit same Vt. Also from the fabrication point of view, it is difficult to create two different doping levels on a substrate

Conclusion

This research paper demonstrated, static and dynamic behavior of all p-organic inverter circuits in DLL and ZVLL configurations, using SG and DG transistors. Dual gate organic transistor exhibited superior performance in terms of Ids, μ, Ion/Ioff, SS and gm, as compared to SG. Appropriate tuning of threshold voltage through the back gate bias on dual gate drive transistor shifts the trip voltage towards Vdd/2, resulting in substantial improvement in noise margin. An increase of 8% and 19% in

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