High-K materials and metal gates for CMOS applications

Abstract

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO₂ by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO₂ which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

Introduction

The incorporation of high-K dielectrics with metal gates into a manufacturable, high volume transistor process is the result of tremendous ingenuity and effort by many scientists and engineers [1]. We review that progress in this article, with an emphasis on the key developments in the high-K/metal gate stack process. We also summarise recent results on incorporation of Ge in the transistor, which appears to provide a viable route to higher performance technology.

It is more than a decade since high-K gate dielectric research for Si-based transistor technology was first reviewed [2], [3]. We begin this review with a brief summary of the scaling issues that drove the incorporation of high-K dielectrics and metal gate technologies. We then discuss the materials chemistry of the high-K dielectrics employed in transistor fabrication. This is followed by a review of the current understanding of the high-K/semiconductor interfacial bonding. Defects, which play an important role in high-K dielectrics, are then discussed. Of course, the electrical performance of the transistor is paramount, and we review the recent developments, including work function control for the transistor gate stack.

The complementary metal oxide semiconductor (CMOS) field effect transistor (FET) made from silicon is the most important electronic device. This has arisen because of its low power consumption and its continuing performance improvement over 40 years following Moore's Law of scaling. This “law” notes that the number of devices on an integrated circuit increases exponentially, doubling every 2–3 years. The minimum feature size in a transistor decreases exponentially each year (Fig. 1).

Until recently the materials and elements used in CMOS technology were very few – Si, O, P, Al, B, H and N. Now the situation has reversed. New materials are being introduced in many areas, from Cu instead of Al for interconnects, low dielectric constant materials such as SiOCH for inter-metal dielectrics, silicides as contact metals, and diffusion barrier materials such as TiN.

The SiO₂ layer used as the gate dielectric is now so thin (∼1.2 nm) that the gate leakage current due to direct tunnelling of electrons through the SiO₂ becomes too high, exceeding 1 A/cm² at 1 V (Fig. 2). This means that the static power dissipation would be unacceptable [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13]. In addition it becomes increasingly difficult to make such thin films, and they become increasingly unreliable. Thus, SiO₂ had to be replaced.

An FET is a capacitance-operated device, where the FET source–drain current depends on the gate capacitance, which is most simply expressed as

$$C=\frac{{\epsilon }_{0}KA}{t}$$

where ɛ₀ is the permittivity of free space, K is the relative dielectric constant, A is the area and t is the oxide thickness. Tunnelling currents decrease exponentially with increasing distance. Hence, the solution to the tunnelling problem is to replace SiO₂ with a physically thicker layer of new material of higher K, as shown in transmission electron microscope images Fig. 3. This will keep the same capacitance, but decrease the tunnelling current. These new gate oxides are called ‘high K oxides’.

For a device designer, as the precise material does not matter, it is convenient to define an electrical thickness of a new oxide in terms of its equivalent silicon dioxide thickness or ‘equivalent oxide thickness’ (EOT)

$$t_{\text{ox}}=\text{EOT}=\left(\frac{3.9}{K}\right)t_{\text{HiK}}$$

Here, 3.9 is the static dielectric constant of SiO₂. The objective is to develop high K oxides to allow scaling to continue to very low EOT values.

The gate leakage problem has been apparent since the late 1990s [14], but the criteria for choosing the oxide were unclear. In about 2001, the choice of oxide had narrowed to HfO₂, but the problems of making HfO₂ into a successful electronic material were great. Nevertheless, the increasing importance the low-power electronics in cell-phones, lap-tops, and portable electronics mean that the problem had to be solved. Low standby power CMOS requires a leakage current of below 1.5 × 10⁻² A/cm² rather than just 1 A/cm². There were many difficulties in manufacturing high K oxides/metal-gate stacks but these were gradually overcome. Intel now manufactures the chips with second generation of high K/metal K stacks [1], [15] and have now implemented high K for FinFET structures as well.

The second critical issue was the realisation that metallurgical problems would limit the introduction of the high K/metal gate stack in an exact replica of the SiO₂ gate process (gate first) [16], and that instead a ‘replacement gate’, ‘dummy gate’, or ‘gate last’ process [15] would need to be used, to limit the exposure of high K/metal gate interface to high temperatures.

In a key early paper, Gusev et al. [17] identified four key problems for successful introduction of high K oxides-

• be able to continue scaling to lower EOTs,

• stop the gate threshold instabilities caused by the high defect densities,

• limit the loss of carrier mobility in the Si channel when using high K oxides,

• control the gate threshold voltage, which resulted in the need for metal gates.

Viewing the Si – gate stack band diagram of a MOSFET (Fig. 4), the gate capacitance is the series combination of three terms, the oxide capacitance, the depletion capacitance of the gate electrode, and the capacitance of the Si channel carriers. These three capacitances add as (Fig. 5).

$$\frac{1}{C}=\frac{1}{C_{\text{ox}}}+\frac{1}{C_{\text{D}}}+\frac{1}{C_{\text{Si}}}$$

As C varies as 1/t, capacitors in series combine as a sum of effective distances. Thus we can define an ‘effective capacitance thickness’ ECT of the whole gate stack as

$$\text{ECT}=t_{\text{inv}}=\text{EOT}+t_{\text{gate}}+t_{\text{Si}}$$

ECT is also known as the inversion thickness t_inv.

The channel capacitance C_Si arises because the 2-dimensional electron gas of carriers in the channel cannot lie infinitely close to its surface, but delocalises a few Angstroms into the Si. This capacitance contribution is intrinsic and cannot easily be changed. High-k dielectric materials are often first evaluated using a MOS capacitor structure, and sunsequently utilising a transistor structure measuring the substrate (depletion) and source/drain (inversion) capacitance (“Split CV”) independently [18], [19].

Previously, the gate electrode was made out of degenerately doped polycrystalline silicon (poly-Si). This is stable at high temperatures and compatible with SiO₂. Poly-Si is a reasonable metal, but it is not a good enough metal as its relatively low carrier density gives a depletion depth of a few Å. In contrast, a good metal has a much higher carrier density and a depletion depth of only 0.5 Å. This depletion effect is removed by replacing poly-Si with a normal metal. The effect on ECT of the replacement of SiO₂ by a high K oxide and poly-Si gate electrode by a metal is shown schematically in Fig. 5. As noted below, the work function of the metal is a critical property to enable proper NMOS or PMOS FET operation.

The ECT is the only thickness that can be measured directly, by capacitance–voltage (CV) methods. On the other hand, EOT can only be estimated by, for example, electron microscopy measurements of oxide thickness, or by back calculating from ECT. EOT is useful, but is not a direct electrical parameter for FETs.

A metal gate material must also be carefully chosen. It is chosen primarily for its work function and its thermal robustness, as discussed in detail in Section 6.