Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Abstract

The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware.

Introduction

Brain functionality is based on the specialised signal processing capabilities of neurons (Trappenberg, 2010). A neuron consists of a cell body (soma) that possesses many input branches called dendrites, which carry information from other neurons. The neuron output (axon) communicates information to other neurons in the form of action potential pulses or spikes. Spikes are transmitted between neurons via weighted synaptic connections (synapses). Each neuron maintains a membrane potential, which is a function of the incoming spike rate, the neural network spatial distribution (network topology) and the synaptic weights (Maass, 1997). A neuron fires (generates an output spike) when the sum of its weighted input spikes exceeds a firing threshold value.

The brain contains an estimated ${10}^{10}$ neuron cells and ${10}^{15}$ synapses arranged in a parallel manner (Gerstner & Kistler, 2002). Large-scale artificial neural networks (ANNs) attempt to emulate (to a degree) the information processing function of the mammalian brain (Jain, Mao, & Mohiuddin, 1996). Researchers have studied and developed various neuron mathematical models to emulate neuron behaviour. Spiking neural networks (SNNs) (Maass, 1997) are a type of ANN, which use the timing of spikes, the network topology and synaptic weights to code information. SNNs offer the possibility of developing biological plausible neuron models and exhibit the ability to quickly adapt and to provide fault-tolerant capabilities (Paugam-Moisy & Bohte, 2009). These attributes, and the ability of SNNs to provide a good solution in partially observable environments and data with uncertainty, make SNNs suitable for implementing resilient classifiers and control applications.

The brain is highly efficient at processing information and tolerating faults. Research aims to harness these efficiencies and to build artificial neural systems that can emulate the key information processing principles of the brain. However, spiking neuron models have become very complex and the number of neurons anticipated for large-scale simulations is significant. Currently, high-performance computing systems are required to perform simulation of large-scale neural networks. Software-based SNNs are too slow to execute large-scale SNN-based algorithms and do not scale efficiently to ever increasing number of neurons. The complexity of inter-neuron connectivity makes it difficult to develop biological-scale SNNs in hardware, where the rapid increase in the ratio of fixed connections to the number of neurons limits the size of the network (Maguire et al., 2007). The traditional bus-based approach does not provide the mechanisms to overcome the SNN interconnection problem. The challenge is therefore to develop a dense synapse/neuron interconnection pattern, implemented in an embedded electronic device with low power consumption, reconfigurable capabilities, intrinsic parallelism and a high level of scalability; however this still remains a significant engineering problem.

Recently, research has focused on the network-on-chip (NoC) interconnect paradigm as a possible mechanism to support SNN scalability. The NoC paradigm replaces the bus-based approach to overcome the problem of wiring and the single point of arbitration. Furthermore, it enables parallel communication of concurrently handled data packets. In the case of SNNs, the NoC paradigm uses an array of routers to provide the communication infrastructure for neuron interconnection. Therefore, the router architecture plays an important role due to the use of the NoC as an interconnection fabric for large-scale SNNs, and demands a good trade-off between power consumption, throughput and traffic congestion, for example:

Power consumption. The NoC router is the communication point to which the neurons are attached. The number of routers increases proportionally with the number of neurons. Therefore, the power consumption for large-scale SNN hardware implementations increases since the major contributor towards power consumption is the interconnection fabric, rather than the neuron itself (Hale, Grot, & Keckler, 2009). The neuron typically has a power consumption approximately six orders of magnitude smaller than the interconnection fabric (Livi & Indiveri, 2009).

Throughput. The router is responsible for managing spike events. SNN traffic patterns are highly asynchronous and non-uniform (Gerstner & Kistler, 2002). Hence, an effective arbitration policy is required. In addition to offering adaptive routing based on the traffic behaviour, a router should also maximise spike throughput, without affecting the traffic performance and without incurring any significant hardware overhead.

Traffic congestion. Although the typical firing rate for a biological neuron is between 10 and 30 ms (Trappenberg, 2010), the number of spike events increases with the number of neurons. The NoC router must achieve real-time performance and offer a low probability of spike packet drop out as the neuron density increases. Therefore, routing algorithms should implement traffic congestion management features.

The authors have investigated and proposed EMBRACE (Emulating Biologically InspiRed ArChitectures in hardwarE), a scalable, mixed-signal embedded hardware SNN device (Harkin et al., 2009). An overview of the EMBRACE framework is presented in Fig. 1. The proposed EMBRACE SNN hardware, which is still to be fully realised, incorporates a low-area/power CMOS-compatible analogue neuron/synapse cell architecture (Chen, McDaid, Hall, & Kelly, 2008). EMBRACE implements inter-neuron connectivity through the use of a digital packet-based NoC communication architecture, illustrated in Fig. 1(a), which provides flexible, time-multiplexed communication channels, scalable interconnect and reconfigurability (Carrillo et al., 2011, Carrillo et al., 2010). The main building block for EMBRACE is the neural tile. The neural tile allows the merging of the analogue neuron/synapse circuitry with NoC digital interconnect to provide a scalable and reconfigurable neural building block. Spike events are passed between neural tiles via the NoC routers. Additional, EMBRACE research incorporates SystemC modelling and SNN NoC traffic analysis (Pande et al., 2010) and an evolvable hardware SNN training platform and configuration toolset (Cawley et al., 2011), as shown in Fig. 1(b).

This paper presents a novel adaptive NoC router which provides the inter-neuron connectivity within the EMBRACE architecture. The novel adaptive NoC router maintains SNN communication and avoids dropped SNN packets by adapting to SNN traffic congestion in large-scale neural network-based hardware computing systems. The adaptability of the proposed router can be described in two dimensions: (1) an adaptive arbitration policy which combines the fairness policy of a round-robin arbiter and the priority scheme of a first-come first-served approach, enabling improved router throughput according to the traffic behaviour presented across the network; (2) an adaptive routing decision module which enables the selection of different router paths to avoid traffic congestion based on pattern traffic and a channel congestion detector.

Therefore, the proposed NoC router is able to sustain the throughput under different spike traffic loads and also adapts to NoC router congestion and broken router connections by reconfiguring the routing topology to select an alternative route. This provides a fault-tolerant capability which is of paramount importance if large-scale SNNs are to be achieved in hardware. Router adaptive behaviour in the presence of applied real-time traffic congestion has been demonstrated on a Stratix II Altera FPGA for a 4×2 router array. Performance results on power and area analysis of the proposed adaptive router, using a 90 nm CMOS technology, indicates the feasibility of using the proposed adaptive NoC router within a scalable EMBRACE hardware SNN architecture.

The remainder of the paper is organised as follows: In Section 2, the motivation for this research and a summary of previous work on SNN-based NoC hardware implementations is presented. In Section 3, the proposed adaptive NoC router architecture incorporated within the EMBRACE architecture is detailed. In Section 4, results and analysis of the proposed adaptive NoC router architecture in terms of area utilisation, power consumption and spike packet throughput are discussed. Additionally, an FPGA-based hardware implementation of the proposed NoC router is presented along with results to validate the router performance. Finally, in Section 5, future trends for large-scale SNN hardware implementations and conclusions are discussed.