A front-end read out chip for the OPERA scintillator tracker

doi:10.1016/j.nima.2003.10.104

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volume 521, Issues 2–3, 1 April 2004, Pages 378-392

https://doi.org/10.1016/j.nima.2003.10.104 Get rights and content

Abstract

Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32-channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto-trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range [0–100] photo-electrons.

In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance.

Section snippets

The OPERA detector

The goal of the OPERA experiment, a massive lead/emulsion target, is to search for the appearance of ν_μ→ν_τ oscillations in the CNGS (CERN Neutrino to Gran Sasso) beam. It exploits nuclear emulsion for the unambiguous detection of the decay of the τ produced in ν_τ interactions. The detector is described in details in Ref. [1]. It is being built on the basis of two supermodules. Each supermodule consists of a target-tracker section where the interaction takes place followed by a muon

Main features of the ASIC

The Read-Out chip is a 32-channel ASIC with individual input, trigger and charge measurement. The ASIC produces a multiplexed output for the 32 individual charge measurements as well as a hit register, signalling all triggered channels.

Preamplifier architecture

The variable gain preamplifier is built around current mirror and switches preceded by a current conveyor. The preamplifier input stage is designed around a “super common base” architecture, whose schematics is shown in Fig. 9. With this architecture, the input impedance is set to a reasonably low value of about $100 Ω$ while keeping small currents circulating in the mirror, and thereby reducing cross-talk.

The common base used as current conveyor is mounted in the feedback loop of a simple

Fast shaper architecture

The fast shaper is directly fed with the mirror output via a $3 pF$ capacitance and is integrated in a $0.1 pF$ charge amplifier. The time constant of integration is set to $10 ns$ to produce a fast signal and a differential input is used to minimize offset dispersion and allow a common threshold for the chip with a minimal spread. The simulated open-loop performances are shown in Fig. 14. The open-loop gain is G₀=220, with a gain bandwidth product $GBW =220 MHz$ and a dominant pole at $W_{0} =1 MHz$ . The phase

Slow shaper architecture

The mirror output is made available as a voltage pulse on the RC integrator and is shaped by a CRRC shaper with a time constant set to minimize the sensitivity to the arrival time. The shaper is included in a Sallen–Key structure. In order to minimize pedestal variation from channel-to-channel slow shaper DC offset dispersion, again a differential input stage has been used. To reduce the offset, the amplifier has a bipolar NPN differential pair on its input stage. The design of this stage makes

PMT readout with the ASIC

A multianode PMT has been used to test the ASIC response to a photoelectron signal. An analog board equipped with 2 ASICs has been designed, assembled and connected to the 64 anode PMT. A set of LEDs have been used to illuminate 8 fibres simultaneously inside a black box.

The trigger signal provided by the ASIC, defined as the logical OR of all 32 channels, allows to record the pulse height distribution of any channel. Fig. 27 shows the pulse height distribution obtained for weak LED pulses,

Summary of performance

Table 1 reports the performance as measured on the 32 channel chip. The FE electronic ASIC designed and tested by both LAL and Bern Group is found to satisfy the OPERA Target Tracker requirements: the preamplifier stage allows to correct for the gain differences of the individual PMT channels up to a factor 3.5 with a good precision; the auto-trigger functionality has been tested and found to be 100% efficient at $0.3 p.e.$ signal level and with a negligible electronic noise; the charge

Acknowledgements

The authors would like to thank M. Dracos as well as E. Baussan, J.-L. Guyonnet, B. Humbert, T-D. Le, D. Staub and J. Wurtz from the IReS group (IN2P3-CNRS), for their support as well as for their upstream work on the multi-anode photomultiplier, plastic scintillators and WLS fibres characterization that drove the design of the ASIC.

References (7)

OPERA Proposal, An appearance experiment to search for νμ→ντ oscillations in the CNGS beam, CERN/SPSC 2000-028,...Status Report on the OPERA experiment”, CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP...
M. Dracos, et al., Plastic scintillator target tracker proposal and studies done at Strasbourg, OPERA-NOTE #26, 16 June...
R. Arnold, E. Baussan, et al., IReS, Results about H7546 Multianode PMT's studies, OPERA-NOTE #30,...

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