N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate
Graphical abstract
Fabrication process of the n-type organic memory devices. Gate and source/drain electrodes were thermally evaporated. The active layer [P (NDI2OD-T2)n] and the tunneling dielectric layer (HSQ) and were deposited by spin-coating. The floating gate layer is composed of Au NP's and reduced graphene oxide.
Introduction
The industrial attraction towards organic electronics results from its potential application as a low-cost replacement for conventional semiconductor. Organic polymers has emerged as a fascinating platform because of their flexibility, light weight and ability to easily cover large areas, they can therefore be seen as semiconducting plastics, leading to a new world of potential applications in electronic devices such as solar cells, light-emitting diodes, and field-effect transistors [1], [2].
Recently, a high-mobility electron-transporting polymer (Polyera™ N2200) was developed, it consists of a naphthalene diimide core (NDI), connected with a bithiophene unit (T-T) [3]. Apart from its high electron mobility 0.1–0.84 cm2 V−1 s−1, this polymer is particularly interesting because of its high solubility in common organic solvents, and its good stability in air [4].
In an attempt to create a new kind of organic memory, several types of memory devices based on organic and polymeric materials have been evaluated. Most of the researches on polymer memory devices are taged on binary datas storage with unipolar polymer semiconductors [5], [6]. The memory window in these devices are constrained by unipolar charge carriers trapping mechanism, and great efforts have been made to develop various kinds of charge trapping layers to get large memory window [7], [8], [9].
Organic field-effect-transistors memory based floating-gate architecture are considered to be a best candidate to reach the ultimate goal of flash memory and this is due to its non-destructive read-out, and the feasibility to be integrated with complementary metal oxide–semiconductor (CMOS) devices [10]. For programming and erasing data files, charges are stored on a conducting (semiconducting) layer called floating gate that is surrounded by a dielectric. The dielectric layer between the floating gate and the organic semiconductor (tunneling layer) should be very thin in order to obtain a sufficiently high electric field allowing the injection (rejection) of charges toward (from) the floating gate. The retention data could be improved by using a thick dielectric layer between floating gate and the gate electrode to prevent the trapped charge carriers leaking back to the channel by increasing the energy barrier (non-volatile memory).
Either then conventional thin-film floating-gate devices, nano-floating gate memories (NFGMs) where the floating gate consists of multiple nanocristal dots [11], [12] or charge trapping defects in an insulator or electrets [13], are excellent candidates due to their remarkable charge retention and high data storage density achieved by a good control of the density of conductive nanosites embedded in dielectric layers. Nevertheless, most of the reported organic floating gate transistors (OFGTs) are fabricated with simple or double floating gates consisting of one or multi layers of metallic nanoparticles fabricated by thermal evaporation or chemical processed synthesis [14], [15] and using almost p type small-molecule organic semiconductors (e.g., pentacene) as an active layers, deposited by thermal evaporation [16], [17].
On the other hand, various materials [18], [19], [20], including, organic molecule [21], [22], graphene [23], [24], graphene oxide [25] and its reduced form [26], [27], have been investigated as a building block in charge trapping memory device, showing that a proper selection of charge-trapping materials and the optimization of their nanostructure (distribution, type and size) are very important to achieve excellent non-volatile memory characteristics [28].
In this paper, we present polymeric N-type organic memory devices based double layer floating gate using reduced graphene oxide (rGO) sheets and gold nanoparticles (Au NP's) on silicon substrates. Specifically, the rGO sheets monolayers which cover more than 60% of the surface and the Au NP's which reach a saturated density of about 1.3 × 1011 cm−2, act as the first and the second floating gates, respectively. Back gate/bottom-contact (BG/BC) OFETs were fabricated with High-mobility N-type semiconducting polymer poly{ [ N, N′ - bis (2 - octyldodecyl) - naphthalene −1,4,5,8-bis (dicarboximide) - 2,6 – diyl ] – alt −5, 5′ - (2, 2′ - bithiophene) } [P(NDI2OD-T2)n] used as the active layer. We used two dielectrics as gate insulators, where Hydrogen Silsesquioxane (HSQ) and silicon dioxide (SiO2) are used as tunneling and controlling dielectrics, respectively. Our devices exhibited reversible counter-clockwise hysteresis with a large memory window of 34 V, write/read/erase/read cycling endurance of 103 times, and a very long extrapolated retention time more than 10 years.
Section snippets
Experimental section
Our devises are based on a bottom gate, bottom contact (BG/BC) OFET configuration, A highly-doped p-type silicon covered with a thermally grown 200 nm thick silicon dioxide was used as the bottom gate electrode and blocking dielectric layer, respectively.
The fabrication process is showed in Fig. 1, substrates were cleaned by sonication in ethanol, isopropanol, for 10 min followed by ultraviolet irradiation in an ozone atmosphere (ozonolysis) for 30 min. We use a piranha solution (H2SO4/H2O 2,
Results and discussion
A single floating gate using only Au NP's, and an N-type organic field effect transistor were also fabricated as a references devices [29], to compare the electrical behavior and to get a better understanding of the influence of the double layer (Au NP's/rGO) floating gate on the memory characteristics.
For a FET device, the threshold voltage Vth is fixed at a constant drain-source voltage VDS. Using a floating gate between the blocking and tunneling layers, charge carriers are trapped from the
Conclusion
We have successfully fabricated high-performance N type organic field effect transistor memory devices by integrating Au NP's and rGO sheet as charge-trapping layers and SiO2/HSQ as a blocking and tunneling layer respectively. The double trapping layers electrically separated from each other, can both provide good trapping ability and suppress the stored charge leakage. Our devices exhibit reliable non-volatile memory characteristics, which include, a large memory window, a long extrapolated
Conflict of interest
The authors declare that they have no conflict of interest.
Acknowledgement
This work has been financially supported in part by the French RENATECH network.
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