Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions
Introduction
The scaling of microelectronic technology faces significant challenges to control the electrical performance and limits the further short-channel-effects (SCEs). A number of new structures have been reported to alleviate these degradation effects. Multi-Gate MOSFETs are promising candidates due to their higher drive current capability, better scaling capability, better Drain induced barrier lowering (DIBL) and immunity against the SCEs [1], [2], [3], [4]. However, even with the actual stage of development of Multi-Gate transistors at nanoscale level, many parasitic effects still persist and affect the device electrical performance. In these devices, the accurate elaboration of the abrupt p–n junctions, created between the channel and the drain/source regions, using extremely high doping concentration gradients can be a difficult task to realize with the current available approaches such as flash annealing [5]. Therefore, new structures and approaches should be developed in order to overcome this challenge and reduce the cost of the fabrication process. In this context, the junctionless design, which is recently proposed and fabricated by Colinge and colleagues, can be considered as an alternative candidate to overcome the undesired high cost fabrication process [5], [6], [7], [8]. The idea behind this design resides in the suppression of the doping concentration gradient, so that only a uniform type doping is obtained which allows suppressing p–n junction regions. Although several research studies have been carried out on the performance improvement of junctionless devices [6], [7], [8], [9], [10], [11], but still a lot of enhancements are required for their applications in reliable digital and analog applications. One of the key areas in improving the performance of junctionless devices is the development of new modified structures to reduce the high series resistance effect, which is associated to the source and drain regions. This latter can be arisen as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance [12], [13]. Therefore, new designs and analytical models of gate-all-around junctionless (GAAJ) MOSFET are required, in order to improve the device performance under critical conditions. In this context, numerous analytical models, numerical simulation and design methodologies have been reported to investigate the GAAJ MOSFET. However, to the best of our knowledge, no design approach based on the junctionless MOSFETs is reported to improve the device behavior for RF and analog applications. In this paper, a new design using the drain and source extensions and its analytical investigation, including RF and analog performance of GAAJ MOSFET, has been presented.
This paper presents a comparative investigation of conventional GAAJ MOSFET and the proposed structure in view of their applications in RF and analog circuit design and also gives an insight to the calculation of its performance parameters. Using 2-D numerical device simulation [14], performances of both devices are investigated and compared on the basis of their characteristic parameters to address the impact of the additional source and drain extensions on GAAJ MOSFET performance.
Section snippets
Modeling methodology
This section presents the modeling of the drain to source current and the small signal parameters including drain/source extensions of a long channel (GAAJ) MOSFET. A schematic structure of the investigated device and the conventional one is shown in Fig. 1. For the conventional (GAAJ) MOSFET, the channel body and the source/drain extensions are uniform heavily doped regions, which can be noted by n+/n+/n+. Whereas for the proposed design, the source and drain extensions are both highly doped
Results and discussion
The analytical I–V characteristics of the investigated GAAJ MOSFET with and without drain/source extensions are plotted in Fig. 2. As expected, by including the highly doped extensions, the drain current is improved. It can be easily observed that GAAJ MOSFET with highly doped extensions has higher current as compared to the conventional GAAJ MOSFET and the analytical results are found to be in close agreement with the numerical simulations. It is to note that the appropriate numerical models
Conclusion
Impact of new design based on S/D extensions has been studied on device efficiency, linearity figures of merit, analog and RF behavior of cylindrical GAAJ MOSFET through extensive analytical investigation. The important conclusion drawn from the results is that the introduction of new highly doped S/D extensions in the GAAJ MOSFET design, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current
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