The effect of series resistance on capacitance–voltage characteristics of Schottky barrier diodes

https://doi.org/10.1016/j.ssc.2005.05.050Get rights and content

Abstract

The capacitance–voltage (CV) and current–voltage (IV) characteristics of the Ti/p-Si Schottky barrier diodes (SBDs) have been investigated taking into account the effect of the interface states and series resistance of the device. The forward CV measurements have been carried out in the range frequency of 0.3–2 MHz (at six different frequencies). It is seen that the forward CV plots exhibit anomalous peaks in the presence of a series resistance. It has been experimentally determined that the peak positions in the CV plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. In addition to, the effect of series resistance on the capacitance is found appreciable at higher frequencies due to the capacitance decreases with increasing frequency.

Introduction

Schottky barrier diodes (SBDs) have been the subject of many investigations due to its presence in the semiconductor devices such as microwave detectors, transistors, solar cells, and also used as test structure in the research and development of semiconductor technology and devices [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13]. But, electrical characteristics of these devices are often influenced by various non-idealities such as an interface states and interfacial oxide layer, interface fixed charges, and series resistance [1], [2], [3], [4], [5], [6], [7], [8], [9], [10]. The series resistance is an important parameter, which causes the electrical characteristics of SBDs to be non-ideal. Usually, the forward bias current–voltage (IV) characteristics are linear in the semi-logarithmic scale at low voltages but deviate considerably from linearity due to effect of parameters such as the series resistance Rs, the interfacial layer and the interface states when the applied voltage is sufficiently large [2], [3]. The parameter Rs is only effective in the curvature downward region (non-linear region) of the forward IV characteristics, but the other two parameters are effective in both the linear and non-linear regions of these characteristics, accompanying change of the Schottky barrier height. Several authors suggested [7], [8] many method which can help to determination of the series resistance, but they suffer from a limitation of the applicability, in this field, to practical devices with the interfacial oxide layer. Norde [7] has proposed a method for evaluation of the Rs from the forward IV characteristics considering for an ideal Schottky diode, namely with n=1, but not for n>1. Sato and Yasumura [8] used a function F(V) similar to that of Norde taking into account that n can be greater than unity. Later approach requires two experimental IV measurements at two different sample temperatures and determination of the corresponding minima of the modified Norde function. Cheung et al. [9] proposed another model and derived the diode parameters from only one single current–voltage measurement. The Cheung's plots are determined from data of the downward curvature region in the forward IV plot which results from the series resistance and the effects of interfacial parameters. Therefore, in this method, it is difficult to determine whether the non-ideality in this region of the forward IV characteristics is caused by only the series resistance or the interface properties. Furthermore, a technique has been developed to determine the series resistance of a non-ideal Schottky barrier diodes using high frequency forward CV and forward IV characteristics by Chattopadhyay and Raychaudhuri [10]. The capacitance of Schottky barrier diodes has been also studied during the last few decades [10], [13], [14], [15], [16], [17], [18], [19], [20]. An idealized capacitance–voltage (CV) characteristic is independent frequency and shows an increase in capacitance with increasing forward voltage [2], [3]. In recent years, some investigations [13], [14], [15], [16], [17], [18], [19], [20] have reported an anomalous peak in the forward bias CV characteristics. The origin of such a peak or this anomalous variation in the forward bias CV plots has been ascribed to the interface states by Ho et al. [15] who compared the CV plot for as deposited and annealed silicide–silicon interface. However, Werner et al. [16] and Bati et al. [20] have shown that the observed peak in the above characteristics is due to the series resistance which arises mainly because of non-ohmicity at the back contact of the device. They have correlated this anomalous variation in the forward bias CV plots to imperfect ohmic back contact that add a contact resistance to the equivalent dc-circuit of the Schottky barrier diodes, and conclude that minority carrier injection depends sensitively on the properties of the ohmic back contact. Then, Wu and Yang [17] have extracted a new formula including substrate resistance and interface state capacitance effect for the metal–semiconductor (MS) structures capacitance by using Shockley–Read statistics, they have suggested that such peaks in their theoretical and experimental CV plots do not originate from substrate resistance but rather from the interface states. On the other hand, Chattopadhyay et al. [10] have shown theoretically that the peak value of the capacitance varies with series resistance and interface state density in the forward bias CV plots of metal–interfacial layer–semiconductor (MIS) Schottky barrier diodes. The aim of this syudy is to investigate experimentally the frequency dependence of the forward capacitance–voltage characteristics of the Ti/p-Si Schottky barrier diode by considering the series resistance effect. Therefore, we have measured the forward CV characteristics of the Ti/p-Si Schottky barrier diode at frequencies changing from 300 kHz to 2 MHz. To determine an accurate value of the series resistance (Rs) of the Ti/p-Si Schottky barrier diode, we have also compared Chenug's model to the model of Chattopadhyay and RayChaudhuri's [10].

Section snippets

Surface potential as a function of applied bias and capacitance–voltage relation

The energy-band diagram of a metal and p-type semiconductor SBD in the presence of a thin interfacial layer and series resistance under the forward bias is shown in Fig. 1. In the figure, Φm is the metal work function, χ the electron affinity of semiconductor, δ the thickness of the interfacial layer, Vi the potential drop across the interfacial layer, Φ0 the neutral level of the interface states measured from the top of the valance band, Vp the potential difference between the Fermi level and

Experimental procedure

The diodes were prepared using mirror cleaned and polished p-type Si wafers with (100) orientation and 5–10 Ω-cm resistivity. The wafer was chemically cleaned using the RCA cleaning procedure [i.e. a 10 min boil in NH4OH+H2O2+6H2O followed by a 10 min boil in HCl+H2O2+6H2O]. Before ohmic contact formed on the p-type Si substrate, the samples were dipped in dilute HF:H2O (1:10) about 30 s to remove any native thin oxide layer on the surface, finally the wafer was rinsed by ultrasonic vibration in

Results and discussion

Fig. 2 shows the experimental semilog-forward and reverse-bias characteristics of the Ti/p-Si SBD. The values of the barrier height Φbp and the ideality factor n of the Ti/p-Si SBD were calculated as 0.677 eV from the y-axis intercepts of the semilog-forward bias IV plot and 1.692 from the slope of the linear region of the semilog-forward bias IV characteristics indicating that the effect of series resistance in this region was not important, respectively [9], [10], [11], [12], [13]. This

Conclusion

We have studied the forward bias capacitance–voltage characteristics of Ti/p-Si SBDs as a function of frequencies, and its current voltage characteristic. The forward-bias CV plot exhibited a peak due to the substrate series resistance Rs. It has been found that the peak value of the capacitance and its position depends on the series resistance and the interface states of the SBD. At high frequency where the influence of interface states decreases, the peak value of the capacitance decreased

Acknowledgements

This work was supported by the Scientific Research Projects Unit of Erciyes University, under project no FBT-04-18 EUBAP.

References (20)

  • V. Mikhelashvili et al.

    Solid-State Electron

    (2001)
  • P. Chattopadhyay et al.

    Solid-State Electron

    (1992)
  • E. Ayyıldız et al.

    Solid-State Electron

    (1996)
  • R.T. Tung

    Mater. Sci. Eng. R

    (2001)
  • H.C. Card et al.

    J. Phys. D

    (1971)
  • S.M. Sze

    Physics of Semiconductor Devices

    (1981)
  • E.H. Rhoderick et al.

    Metal–Semiconductor Contacts

    (1988)
  • A.M. Cowley et al.

    J. Appl. Phys.

    (1965)
  • H. Çetin et al.

    Semicond. Sci. Technol.

    (2004)
  • H. Norde

    J. Appl. Phys.

    (1979)
There are more references available in the full text version of this article.

Cited by (0)

View full text