Elsevier

Solid-State Electronics

Volume 49, Issue 11, November 2005, Pages 1734-1744
Solid-State Electronics

Si nanocrystals by ultra-low-energy ion beam-synthesis for non-volatile memory applications

https://doi.org/10.1016/j.sse.2005.10.001Get rights and content

Abstract

In this work, we show how to manipulate two-dimensional arrays of Si NCs in thin (⩽10 nm) SiO2 layers by ultra-low-energy (⩽1 keV) ion implantation and subsequent thermal annealing. The influence of implantation parameters (dose, energy), annealing conditions (temperature, duration, ambient) and oxide thickness on the NCs characteristics (position, size, density) is reported. Particular emphasis is placed upon post-implantation thermal treatments performed in nitrogen-diluted-oxygen ambient that significantly improve the integrity of the oxide and allow for the fabrication of non-volatile memory devices operating at low-gate voltages. Thermal oxidation in N2-diluted-O2 of high-temperature pre-formed silicon NCs has been also examined and modeled using an extended three-dimensional Deal–Grove model. This model reveals that stress effects, due to the deformation of the oxide, slow down the chemical oxidation rate and lead to a self-limiting oxidation of NCs. The model predictions are in agreement with the experimental results.

Introduction

By exploiting the benefits (robustness and fault-tolerance) of a charge storage distribution, nanocrystal (NC) MOS memory devices offer an attractive alternative for overcoming the scaling limitations of conventional floating-gate semiconductor memories [1], [2]. To achieve reliable devices and avoid fluctuations in device performance not only the NCs characteristics (size, density, interspacing) but also their location inside the gate dielectric have to be well controlled. In particular, a fine control of the thickness of the dielectric layer (injection oxide) separating the NCs and the substrate is absolutely required since a change of less than 1 nm affects dramatically the programming properties (write/erase times and voltages) and data retention of the devices. Among the different technological routes [1], [2], [3], [4] explored the last few years for generating NCs in the gate oxide of MOS devices, the ion-beam-synthesis (IBS) technique has received substantial attention due to its flexibility and manufacturing advantages. The potential of this technique for NC-based-memories operating at low voltages has been recently enhanced through the synthesis in the ultra-low-energy (ULE) regime (typically 1 keV) of single Si-NC layers in thin SiO2 films [2], [5]. In the present study, we show how to manipulate and control the depth-position, size and density of two-dimensional (2D) arrays of Si NCs fabricated in SiO2 films (⩽10 nm) by ULE-IBS. We examine the influence of oxide thickness, implantation parameters (energy, dose) and annealing conditions (temperature, time, ambient –N2 versus N2 + 1.5% O2) on the NCs characteristics, oxide quality, and charge storage properties of the resulting NC gate dielectrics. Specific experimental methods recently developed to characterize the NCs populations have been used. They include transmission electron microscopy (TEM) Fresnel imaging for the evaluation of the distances and widths of interest [6], and spatially resolved electron energy loss spectroscopy (EELS) using the spectrum-imaging mode of a scanning transmission electron microscope (STEM) to measure the size distribution and density of the NCs population [7]. Photo-luminescence (PL) spectroscopy is herein introduced as a tool for monitoring oxide quality recovering induced by thermal treatments in oxidizing atmosphere.

Section snippets

Experimental details

Six sets of samples have been examined. All sample details are summarized in Table 1. Each set is characterized by three parameters: nominal oxide thickness, implantation energy and dose. In Set 1, the dose was kept constant and the energy was varying from 0.65 to 5 keV. In Set 2, the Si implantations were carried out using different dose-energy combination extracted from TRIDYN [8] simulations in such a manner that the peak of concentration of implanted atoms always reached 35 at.% (in SiO2).

Tuning of the NCs position

For tuning the location of the NCs layer within the SiO2 layer, our first attempt was to vary the implantation energy according to the conditions of Set 1 samples. As the ion energy increases from 1 to 3 keV, the NCs layer shifts deeper in the SiO2 layer, i.e. closer to the Si/SiO2 interface (see Fig. 1(a)). Surprisingly, no NCs are detected for 5 keV implantation and HREM imaging (not shown) reveals an unusual roughness [10] of the SiO2/Si interface. In order to compensate the decrease of the Si

Thermal oxidation of NCs: Experimental results and modeling

A systematic experimental study and modeling of the Si NCs oxidation has been performed and is detailed in Ref. [14]. We have chosen to study the oxidation process in the case of Set 6, i.e. for low implanted dose (1016 cm−2) for which a high density of well-separated spherical NCs are observed after annealing under N2 (see Fig. 4). The thermal budget that has been used here for studying the NCs oxidation, i.e. 900 °C for some hours, is high for advanced CMOS fabrication but necessary to detect a

Oxide integrity: a link between PL, TEM and electrical characterization

In addition to NCs characteristics (size, density and position with respect to the electrodes), several conditions are necessary for an optimum electrical behaviour of the devices, including crystallinity of nanoparticles, saturation of surface bonds, and SiO2 integrity. Various implantation-damage related defects (dangling bonds, excess silicon, E’ centers, etc.) strongly affect the integrity of the oxide, and thus, the memory characteristics of the devices. In particular, Si atoms in excess

Electrical characterization

The electrical properties of ULE-IBS NCs gate dielectrics are strongly related to the structural characteristics of the NCs layers and the integrity of the surrounding oxide [13], [32], [33], and therefore, to the process parameters reported here above (implantation dose and energy, annealing regime, oxide thickness). For example, with implantation energy increasing, the electric field needed for effective charging decreases and the magnitude of the flat-band voltage shift, ΔVFB, increases [32]

Conclusion

In this work, we have shown how to control the characteristics of 2D arrays of Si NCs embedded in thin SiO2 layers. The injection distance can be tuned from 8 to 2 nm by a judicious combination of ion beam energy and initial SiO2 thickness. The NCs surface density and coverage can be controlled by the implantation dose even if the efficient range is small. Increase in memory window is observed when increasing implant energy, NCs density up to the coalescence threshold and annealing under

Acknowledgements

This work was supported by the EC through the Growth project G5RD/2000/00320–NEON (Nanoparticles for Electronics). The authors want to thank V. Soncini from ST Microelectronics Agrate for the oxidized wafers, M. Tencé and C. Colliex from LPS/Orsay for the PEELS/STEM images and M. Respaud from LNMO-INSA, Toulouse for its “numerical” support.

References (36)

  • P. Normand et al.

    Nucl Instrum Methods Phys Res B

    (2004)
  • M. Carrada et al.

    Mater Sci Eng B

    (2003)
  • C. Jeanguillaume et al.

    Ultramicroscopy

    (1989)
  • W. Möller et al.

    Nucl Instrum Methods Phys Res B

    (1984)
  • Y. Chen et al.

    Microelectron Eng

    (2001)
  • E. Degoli et al.

    Surf Sci

    (2000)
  • C. Ternon et al.

    Physica E

    (2003)
  • J. De la Torre et al.

    Opt Mater

    (2005)
  • P. Dimitrakis et al.

    Mater Sci Eng B

    (2003)
  • P. Normand et al.

    Microelectron Eng

    (2004)
  • P. Dimitrakis et al.

    Solid-State Electron

    (2004)
  • S. Tiwari et al.

    Appl Phys Lett

    (1996)
  • G. Ammendola et al.

    J Vac Sci Technol B

    (2002)
  • Y.C. King et al.

    IEEE Trans Electron Dev Meet

    (2001)
  • G. Ben Assayag et al.

    Appl Phys Lett

    (2003)
  • P. Dimitrakis et al.

    Materials and processes for nonvolatile memories MRS

    (2005)
  • C. Bonafos et al.

    J Appl Phys

    (2004)
  • M. Perego et al.

    J Appl Phys

    (2004)
  • Cited by (0)

    View full text