Multi-gate devices for the 32 nm technology node and beyond

doi:10.1016/j.sse.2008.04.018

Solid-State Electronics

Volume 52, Issue 9, September 2008, Pages 1291-1296

https://doi.org/10.1016/j.sse.2008.04.018 Get rights and content

Abstract

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V_T statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Introduction

FinFET-based multi-gate (MuGFET) devices have been the topic of many publications over the last decade [1], [2], [3]. The benefits of these devices are very clear: reduced short channel effects, leakage currents, V_T dopant fluctuations and possible higher mobility due to the undoped channels. Recently [4] it has also been demonstrated that these devices can be used for large-scale integration and that digital MuGFET circuits can show superior performance over planar bulk devices. In the first section of this paper, we will briefly discuss the benefits of using MuGFET from the intrinsic transistor performance point of view. The main part of the paper will describe the technological challenges. The last part will briefly give an overview of the performance of circuits fabricated in MuGFET technology.

Section snippets

Benefits of MuGFET devices

Fig. 1 shows a SEM view of a typical MuGFET transistor. The device consists of a channel formed in a Si fin and a self-aligned gate wrapped around the thin Si fin. In this device, the current flow is still horizontal while the sidewalls of the dry-etched Si fin are used as conducting channels. Due to the fact that the gate is wrapped around a tiny fin, the electrostatic control of the gate on the channel is enhanced leading to better immunity against short channel effects (SCE).

The fin width is

Technological challenges

MuGFET fabrication follows a quite conventional Si processing. However, specific process steps will require additional restrictions, e.g. fin critical dimension (CD) control. Next to that, new process modules such as selective epitaxial growth of Si (SEG) will be needed.

In the next part of this section we will present the technological challenges related to the processing of MuGFET devices. Topics like device scaling, work function tuning, access resistance and strain engineering will be

Circuit performance

The Shallow Trench Isolation (STI) free isolation process for MuGFET devices on SOI allows fabricating high density SRAMs (Fig. 11). SRAM cells with dimensions down to 0.314 μm²[22] and even 0.274 μm²[23] have been demonstrated. The latter cell, having a TaN based gate stack, showed a high static noise margin of 216 mV at 1 V with devices having a L_GATE = 37 nm. At the same time, improved OPC for CD control and integration of SRAM and logic circuits was studied.

In [4] a MuGFET inverter delay of 13.9 ps

Conclusions

The MuGFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled beyond the 32 nm technology node. In this paper we have addressed the benefits of these devices and a number of integration challenges. Next to that, we have briefly discussed the potential of these devices for large-scale integration.

Acknowledgements

The authors would like to thank the people working in the litho, etch and SEG development groups, the material characterization group, the IMEC pilot line and measurements labs.

This research is supported by the IMEC EMERALD IIAP program and the European Commission’s Information Society Technologies Program under PULLNANO project Contract No. IST-026828.

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View full text

Multi-gate devices for the 32 nm technology node and beyond

Abstract

Introduction

Section snippets

Benefits of MuGFET devices

Technological challenges

Circuit performance

Conclusions

Acknowledgements

FinFet – a self-aligned double-gate MOSFET scalable to 20 nm

IEEE Trans Electron Dev

Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering

VLSI Technol Symp

Pi-gate SOI MOSFET

IEEE Electron Dev Lett

A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay large-scale integrated high performance digital circuits and SRAM

VLSI Technol Symp

FinFET design considerations based on 3-D simulation and analytical modeling

IEEE Trans Electron Dev

Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography

VLSI Technol Symp

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficienty

IEDM Tech Digest

Tall triple-gate devices with TiN/HfO2 gate stack

VLSI Technol Symp

Jpn J Appl Phys

Threshold voltage modulation in FinFET devices through arsenic ion implantation into TiN/HfSiON gate stack

SOI Conference