PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations

Abstract

This paper reports recent progress in partially depleted (PD) SOI MOSFET modeling using a surface potential based approach. The new model is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including floating body simulation capability, parasitic body currents and capacitances. A nonlinear body resistance model is included for accurate characterization and simulation of body-contacted SOI devices. The PSP-SOI model has been verified using test data from 90 nm to 65 nm PD/SOI processes.

Introduction

In recent years partially depleted SOI technology has become the mainstream technology for low-power, high performance CMOS ULSI applications [1], [2]. Successful use of SOI technologies requires a physics-based SOI MOSFET compact model to serve as the bridge between the manufacturing process and circuit design. Such a model must faithfully reproduce the device characteristics responsible for the advantages provided by SOI technology, such as reduced junction capacitance, elimination of the body effect in stacked devices (e.g., nMOS transistors in NAND gates), dynamic threshold voltage shifts associated with the floating body effect (FBE), and the corresponding increase of the $I_{\text{on}}/I_{\text{off}}$ ratio which is beneficial for low-power CMOS applications.

In addition to the traditional requirements imposed on SOI compact models, aggressive scaling of the gate oxide thickness to 2 nm and below introduces gate-tunneling current components that cause device performance degradations [3]. The importance of gate-tunneling currents is common to both bulk and SOI devices. However, the presence of a floating body in SOI devices requires physical modeling of electron tunneling from valence band (EVB), which is usually not critical for bulk MOSFET models.

For both bulk and SOI CMOS technologies, the reduction of power supply voltage to about 1 V means that the moderate inversion region becomes fractionally larger part of the overall voltage swing [4] and needs to be modeled accurately using either inversion charge based [5], [6] or surface potential based [7], [8], [9], [10] compact models. The latter are also capable of a physics-based description of accumulation region behavior and overlap capacitances, which is important for accurate simulations of advanced CMOS circuit performance [11]. Consequently, one of the advanced surface potential based models (PSP) has been adopted as the new industry standard [12] for bulk MOSFETs. Both threshold voltage based [13] and surface potential based SOI models have been published [14], [15], [16]. Reflecting the state-of-the-art of bulk CMOS modeling in the previous decade, as summarized in [17], the PSP-SOI model brings into the SOI realm the advantages of recent work on the development [12], [18] and verification [19] of surface potential based bulk MOSFET models.

This paper addresses exclusively the modeling of partially depleted SOI devices. With the reduction of silicon film thickness one may encounter transition to full depletion (FD) mode of operation at least for some terminal voltages. The dynamic depletion model describing this behavior will be presented separately. Experimental data used in the present study do not exhibit this behavior.

PSP-SOI shares the non-iterative algorithm for the surface potential calculations used in PSP and is valid for high forward bias of source/drain junctions that can be encountered in the floating body SOI devices. It also shares PSP’s physics-based formulation and descriptions of small geometry effects, which came from merging the best features of SP [7] and MM11 [20]. In particular, this assures complete Gummel symmetry, including the recent requirements imposed on compact models in the presence of tunneling and impact ionization currents [21].

PSP-SOI [22] differs from SP-SOI [16] in several critical aspects. In particular, while the mobility description remains the same, the velocity saturation model is changed to that of PSP and allows modeling of higher-order derivatives at zero drain-to-source bias ($V_{\text{DS}}=0$) [19]. The same applies to quantum-mechanical corrections, channel length modulation and several other short-channel effects which are modeled following the PSP approach. The EVB tunneling model of PSP-SOI is a further advance as is the much more extensive comparison with experimental data. PSP-SOI also contains a detailed surface potential based nonlinear body resistance model. The new model PSP-SOI is implemented in Verilog-A and has been verified by fitting measurement data from 90 nm to 65 nm PD/SOI processes. Simulation results are also presented to illustrate convergence and specific features of the model using parameter sets representing the 90 nm and 65 nm technologies.

This paper proceeds as follows: Section 2 describes the modeling of various body current components that are important in capturing the floating body effect of SOI devices. Self-heating is analyzed in Section 3 and is followed by a presentation of nonlinear body resistance model in Section 4. The noise modeling of PD/SOI MOSFETs is presented in Section 5. In Section 6, typical fitting results on short-channel floating body PD/SOI devices are presented.