Elsevier

Journal of Systems Architecture

Volume 55, Issues 7–9, July–September 2009, Pages 387-395
Journal of Systems Architecture

Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

https://doi.org/10.1016/j.sysarc.2009.07.002Get rights and content

Abstract

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.

Introduction

On-chip interconnect architectures, used in current SoCs to integrate processing elements (PEs), are based on shared-medium bus-based schemes [1], [2], [3], [4]. For large SoCs, the bus-based schemes become limited because they are inherently non-scalable and produce a huge communication overhead that affect the performance and increase the energy consumption. New on-chip interconnects that are flexible as well as energy efficient are required. Recently, to meet these requirements, Networks-on-Chip (NoCs) paradigm has been proposed as a solution for the interconnect problem in SoCs [5]. The main objectives are to satisfy quality of service requirements, to optimize the resources usage and to minimize the energy consumption by separating the communication from the computation [6].

Different on-chip interconnect architectures based on packet switching have been studied and adapted recently for SoCs. The on-chip interconnect architecture specifies the structure in which switches and PEs are connected together. Examples of these architectures are Fat-Tree (FT) [7], 2D mesh [8], Ring [9], Butterfly Fat-Tree (BFT) [10], Torus [5], Spidergon [15], and Octagon [16]. Recently, a new architecture, based on the Wk-recursive networks, was proposed in [12], [13]. Since this architecture has many attractive properties, such as high degree of regularity, symmetry and efficient communication, WK-recursive networks have received considerable attention in parallel computing community [31], [32], [33]. In addition to these interesting properties that suit NoCs, for any specified degree, it can be expanded to an arbitrary level without reconfiguring the edges. A detailed analysis was proposed in [12], [13] to compare the WK-recursive architecture with the 2D mesh architecture in terms of several performance metrics such throughput and for a variety of load scenarios using the Pareto model as a traffic generator. However, emerging SoCs for mobile systems are typically battery-based systems and have to be energy and area efficient. The energy consumption as well as the area requirements for this on-chip interconnect should be evaluated and compared with the other common on-chip interconnect architectures.

In this paper, simulations are conducted and results are reported to compare the energy consumption of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, FT, and BFT, using a variety of load and traffic models including CBR (Constant Bit Rate), Exponential, and Pareto traffic sources. In other words, the main objective of this paper is to compare the energy consumption and area requirements of these on-chip interconnects and study the influence of the application traffics by varying the traffic rate (from light traffic to heavy traffic). The simulation results are reported and show that the average energy consumption increases linearly as the traffic load increases. On-chip interconnects with more links between a source and a destination pair have greater average energy consumption at heavy traffic. For example, WK interconnect shows highest energy consumption compared to the other architectures in heavy traffic, though it provides higher throughput and lower latency as presented in [12]. Moreover, we investigate factors that influence on the energy consumption and the results show that the average number of hops is the most important factor. A higher level methodology to compare the area requirements of these on-chip interconnect architectures is also presented. The reported results show that the buffer area significantly dominates the logic within the switches. Moreover, on-chip interconnects with more links have higher silicon area requirements, while they achieve high throughput and low latency [12], [23].

The rest of the paper is organized as follows. In Section 2, we briefly survey existing work that compare on-chip interconnect architectures especially in terms of silicon area requirements and energy consumption. Section 3 presents the simulation methodology and reports the obtained results. Conclusion and future work are presented in Section 4.

Section snippets

Background and related work

Recent NoC architectures have been studied and compared for different performance metrics. For example, in [17] a simulation based approach using the ns2 simulator was used to analyze a NoC mesh interconnect. It is based on the CLICHE (Chip-Level Integration of Communicating Heterogeneous Elements) [8]. The network simulator ns2 was used to construct the topology and generate different traffic scenarios using the Exponential traffic generator. Common network performance metrics such as drop

The simulation methodology

In this section, we will analyze and compare the energy consumption as well as the area requirements of the WK-recursive interconnect with five on-chip interconnects: 2D mesh, Spidergon, FT, BFT, and Ring. The simulator developed in [13], [17], [23] is used in this evaluation and is based on the discrete event driven simulator ns2 [24]. The objective of using ns2 is to rapidly explore the performance of network protocols by using its facilities to describe network topology (fixed or mobile),

Conclusion and future work

In this paper, we quantitatively compared and characterized the average energy consumption of the WK-recursive architecture with five on-chip interconnect architectures for different communication load and traffic models. We investigated the effects of load and traffic models and the obtained results show that traffic models and load that end components or PEs has a direct effect on the energy consumption. In these results, WK-recursive architecture generally has higher energy consumption at

Mohamed Bakhouya received his Ph.D. degree in 2005 in computer science from the University of Technology of Belfort-Montbeliard (UTBM), France. From 2001 to 2006 he was lecturer at the computer science department of UTBM. During 2006-2008 he was a research scientist at the George Washington University, ECE department, High Performance Computing Laboratory. He is currently a research sientist and lecturer at the University of Technology of Belfort-Montbeliard. His research interests include

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    Mohamed Bakhouya received his Ph.D. degree in 2005 in computer science from the University of Technology of Belfort-Montbeliard (UTBM), France. From 2001 to 2006 he was lecturer at the computer science department of UTBM. During 2006-2008 he was a research scientist at the George Washington University, ECE department, High Performance Computing Laboratory. He is currently a research sientist and lecturer at the University of Technology of Belfort-Montbeliard. His research interests include distributed and parallel algorithms, mobile computing, ubiquitous and pervasive computing, artificial intelligence, grid computing, System/Network-on-Chip.

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    Currently I am research scientist and lecturer at the University of Technology of Belfort Montbeliard, France.

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