The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

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Abstract

The design of embedded systems is being challenged by their growing complexity and tight performance requirements. This paper presents the COMPLEX UML/MARTE Design Space Exploration methodology, an approach based on a novel combination of Model Driven Engineering (MDE), Electronic System Level (ESL) and design exploration technologies. The proposed framework enables capturing the set of possible design solutions, that is, the design space, in an abstract, standard and graphical way by relying on UML and the standard MARTE profile. From that UML/MARTE based model, the automated generation framework proposed produces an executable, configurable and fast performance model which includes functional code of the application components. This generated model integrates an XML-based interface for communication with the tool which steers the exploration. This way, the DSE loop iterations are efficiently performed, without user intervention, avoiding slow manual editions, or regeneration of the performance model. The novel DSE suited modelling features of the methodology are shown in detail. The paper also presents the performance model generation framework, including the enhancements with regard the previous simulation and estimation technology, and the exploration technology. The paper uses an EFR vocoder system example for showing the methodology and for demonstrative results.

Introduction

The design of embedded systems is in a highly competitive context. The translation of an efficient design into a successful product highly depends on becoming the first product in the market with new complex functionalities fulfilling tight performance constraints, and at an affordable price. In this scenario, the task of system engineers becomes challenging. They have to do an early assessment of the design alternatives since about 90% of the overall cost is determined at the first stages of the design [1]. At the same time, a right assessment becomes difficult due to the complexity of applications and platforms. Performance depends on a diverse set of factors, such as the architecture of the software application, the architecture of the hardware platform, how the application functionalities are executed by the processing resources of the platform, and many parameters such as cache sizes, memory sizes, etc. This makes Design Space Exploration (DSE) a key design activity [2] in ESL design for enabling such an early assessment.

A DSE framework has three main requirements: (1) a specification methodology suitable for Design Space Exploration (DSE), as well as for other ESL design activities (i.e., verification and SW synthesis); (2) techniques and tools able to produce fast and sufficiently accurate performance metrics; and finally (3) exploration strategies able to prune a potentially huge design space.

An important number of methodologies relying on different techniques for performance estimation and specific exploration strategies have been proposed. Some of them have also enabled a high-level input, based on a model which captures the system architecture and main system parameters. Specifically, there has been an effort on starting from models based on the Unified Modeling Language (UML) [3], supported by specialized profiles, such as SysML and MARTE [4]. These approaches effectively joined Model Based Design (MBD) with Electronic System Level (ESL) design. However, these methodologies present a number of drawbacks yet. UML/MARTE methodologies do not present all the features required for DSE. Specifically UML/MARTE models have to be edited along DSE iterations, which slows down the exploration, because they do not provide mechanisms to model and define the design space in terms of the parameters, architectures and architectural mappings that the user wants to explore, and in terms of the performance metrics which need to be constrained. Second, traditional simulation-based performance estimation technologies are too slow for exploring DSE systems, while analytical approaches have to sacrifice much accuracy. Third, the exploration strategies propose implementations tightly coupled to the solution of a specific optimization problem, which makes those DSE frameworks specific and difficult to extend with enhancements on both, performance estimation and exploration techniques. Out of the UML/MARTE context, and even from the model-based design context, other works, explained later on in Section 2, have provided advanced features for DSE including some of the aforementioned ones. This work has combined, extended and applied many of them to an UML/MARTE modelling context.

Two main approaches to DSE can be distinguished attending the way a design point is evaluated, those based on analytical techniques and those based on simulation [5]. Analytical approaches relying on worst-case workloads and predictable architectures are suitable for applications which require a high degree of confidence on constraint fulfilment, e.g. time critical or safety critical applications. However, these approaches often lead to more inefficient design solutions and their applicability is limited by modelling constraints required for the application of the analytical model.

In contrast, a simulation-based DSE approach, like the one proposed in this paper, enables more accurate estimations, and makes feasible the assessment of performance of complex application models and advanced architectures, where the development of an analytical model gets too complex. Therefore, simulation-based DSE is a suitable solution in domains such as consumer electronics, where it is necessary to find efficient designs in an affordable design time for applications with QoS requirements and time-critical (but not safety critical) constraints, on top of devices with complex architectures (multiprocessor, memory and communication hierarchies, etc.).

This paper presents the UML/MARTE Modeling and Design Space Exploration (DSE) framework for embedded systems, developed in the context of the COMPLEX project [6][7]. In short, we will refer to this framework as COMPLEX UML/MARTE DSE framework, to distinguish it from other concepts, techniques and tools developed in the COMPLEX project, e.g., which include for instance a Matlab/Simulink front-end, or the support of power management, and which are not part of the work presented in this paper.

Distinctive aspects of the COMPLEX UML/MARTE methodology are the following:

  • It fits the general MBD-based DSE flow sketched in Fig. 1. In this approach the user input is a system model supporting component-based modelling and separation of concerns, and containing all the required information for the DSE activity.

  • It supports a MBD model of the system working environment. This way, more efficient solutions are found by tuning them to the specific working environment. The integration of the MBD environment model on an accurate simulation-based performance model is automated.

  • The model is captured once and it can be reused for other ESL design activities, e.g. SW synthesis (single source approach). In this sense, the model serves also as a specification.

  • From the specification, an executable and configurable performance model is automatically generated.

  • The estimated performance associated to each explored design point is obtained by relying on native simulation, much faster than virtualization or Instruction Set Simulators (ISS).

  • The technology supports SW and HW estimation; it considers the impact of different communication types (SW–SW, SW–HW, etc.,); and supports a generic, RTOS independent API, which enables the analysis of different architectural mappings without the need to generate the complete SW stack in each executing node or to synthesize the HW.

  • The performance estimation model and the exploration tool are kept separated and integrated through a XML-base interface which enables a modular DSE framework.

In previous work the UML/MARTE methodology for modelling the system [9] and the stimuli environment [10] has been presented. In [11], the automatic generation from the UML/MARTE specification of a performance executable and configurable model was explained. This performance model relies on the SCoPE technology [14], [15], [16]. The integration of the IP-XACT format in the code generation [12], and its support as part of the SCoPE front-end was explained in [13]. In [20] M3SCoPE, which connected the performance estimation tools (SCoPE) and the exploration tool (M3Explorer) [21], was explained. Performance estimation technology has been improved, so SCoPE+ now supports the performance estimation of different architectural mappings from the same Platform-Independent model (PIM) without the need to generate the SW stack in each node [17]. Moreover, a fast performance estimation technique for the estimation of performance of the functionality mapped to HW was developed in [19].

In this paper, a complete overview of the COMPLEX UML/MARTE-based methodology for DSE is given. Moreover, the paper contributes new aspects not addressed in previous work, specifically:

  • The MOST exploration tool is shown as a main component of the flow which is smoothly integrated through an XML based interface. MOST enables the analysis of a huge design space, which can include different scenarios, without requiring the edition of the environment model along the DSE loop.

  • An extended example (vocoder instead of coder), showing more significant features and capabilities of the methodology, such as the capability to explore distinct mappings and considering different scenarios.

  • The integration of the HW estimation library in SCoPE+.The co-simulation of the system with the SystemC environment.

The rest of the paper is structured as follows. In Section 2, the state of art is reviewed. Section 3 explains the UML/MARTE modeling:modelling methodology. Then Section 4 explains the generation of the SCoPE+ executable and configurable performance estimation model and introduces MOST and its integration in the flow. Section 5 provides experimental results. Section 6 provides the main conclusions of this work.

Section snippets

Modeling methodologies in UML/MARTE and model-based DSE

Despite the relative recent development of the MARTE profile, several works have proposed UML/MARTE based methodologies. The MARTE profile is an OMG standard that offers a rich set of extensions specifically suited for the specification of embedded real-time systems. MARTE enables building models containing detailed information about the application, about the platform attributes and its architecture, for enabling performance analysis.

Gaspard2 [22], [23] is a design environment for

Basic features

The system Modeling methodology described in this paper covers the main demands addressed at the end of Section 2.1. It follows a component-oriented approach; it is software centric; and it follows Model Driven Architecture (MDA) concepts. The design exploration and implementation activities are developed around the model, which is also amenable to be used for static analysis and for generating documentation. The methodology also enables modelling and estimation of implementing application

Complex toolset

The COMPLEX modelling methodology is supported by the COMPLEX Eclipse Application (CEA) tool which provides an integrated framework for the HW/SW co-design and design exploration. This tool is integrated within the Eclipse framework and makes extensive use of the Eclipse Modeling Framework (EMF) [77] and Model-to-Text facilities [78]. This section aims at providing a flavour of the most important features of the CEA tool in supporting the COMPLEX modelling methodology.

The CEA tool (shown in

Experimental results

In order to show the capabilities and advantages of the proposed methodology, a design space exploration of the EFR vocoder model introduced in the previous sections has been done. Indeed, the model was modified to show a larger and more interesting design space. It was decided to fix the mapping of some components to avoid the exploration of equivalent design points and to explore working frequencies independently, per processor code. The reason for this was that, in one initial trial, it was

Conclusions

This paper has presented the COMPLEX UML/MARTE based methodology for Design Space Exploration of Embedded systems, a key activity for the design of complex embedded systems. The methodology integrates key and mature technologies in modelling, performance estimation and exploration.

A UML/MARTE modelling methodology, which integrates advanced features specifically suited for DSE has been presented. The methodology consolidates key aspects for industrial modelling-based design, i.e.

F. Herrera got his Ph.D. in Electronics from the University of Cantabria in 2009, where he accumulated more than eleven years of research experience on ESL design topics (e.g., system modelling specification, automatic embedded software generation. He has participated in several European projects, and in particular he was the technical coordinator of the team of the Microelectronics Enginering group of the University of Cantabria (UC/GIM) during two years. Currently, he is a post-doctoral

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    F. Herrera got his Ph.D. in Electronics from the University of Cantabria in 2009, where he accumulated more than eleven years of research experience on ESL design topics (e.g., system modelling specification, automatic embedded software generation. He has participated in several European projects, and in particular he was the technical coordinator of the team of the Microelectronics Enginering group of the University of Cantabria (UC/GIM) during two years. Currently, he is a post-doctoral researcher in the Electronic Systems group of the Royal Institute of Technology (KTH) in Stockholm, Sweden.

    H. Posadas received the master degree in Telecommunication Engineering in 2002 from the University of Cantabria, the degree in Informatics from the UNED in 2006, and the Ph. D in Electronics from the University of Cantabria in 2011. He is currently an assistant teacher at the Electronics Technology, Automatics and Systems Engineering Department. His research interests include co-design methodologies for embedded systems, focusing on high-level modelling, performance estimation, and SW synthesis.

    P. Peñil received the master degree in Physics in 2002 and the master degree in Telecommunication Engineering in 2009 from the University of Cantabria, Santander, Spain. His research interest covers co-design methodologies based on UML by applying the MARTE profile.

    E. Villar got his Ph.D. in Electronics from the University of Cantabria in 1984. Since 1992 is Professor at the Electronics Technology, Automatics and Systems Engineering Department of the University of Cantabria where he is currently the responsible for the area of HW/SW Embedded Systems Design at the Microelectronics Engineering Group. His current research interests cover system specification and design, MpSoC Modelling and performance estimation using SystemC and UML/MARTE.

    Francisco Ferrero received his Master of Science degree in Telecommunications Engineering from the Carlos III University of Madrid. Mr. Ferrero is GMV́s project manager of COMPLEX project. FERRERO has participated in several EU-projects (CHESS, nSafeCer, COMPLEX) and research ESA projects like (HWSWCO, COrDeT2, OBCP-BB) centred on MDE technologies. He is experienced in model-based technologies in the context of embedded critical software and tool development for supporting MDE methodologies based on the Eclipse framework.

    Raúl Valencia received his Master of Science degree in Computers engineering degree from the Polytechnic University of Madrid (UPM). Mr. Valencia is a GMV’s project engineer that has participated in MDE technologies related projects (EU-FP7’s COMPLEX project, ESA’s OBCP-BB project) mostly centred in analysis and design of HW/SW real-time systems. His experience includes the design of embedded real-time systems using UML’s MARTE profile and the development of Eclipse based tools supporting MDE methodologies.

    G. Palermo received the M.S degree in Electronic Engineering, in 2002, and the Ph.D degree in Computer Engineering, in 2006, from Politecnico di Milano. He is currently an assistant professor at Department of Electronics and Information Technology in the same University. Previously he was also a consultant engineer in the Low Power Design Group of AST - STMicroelectronics working on network on-chip. His research interests include design methodologies and architectures for embedded systems, focusing on power estimation, on-chip multiprocessors and networks on-chip.

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