Abstract
A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also local memories and constraints on the size of available memories. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.
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Y. Wong and J.M. Delosme, “Optimization of computation time for systolic arrays,” in Proc. Int. Conf. Parallel Processing, Sept. 1988.
J. Teich and L. Thiele, “Partitioning of processor arrays: A piecewise regular approach,” INTEGRATION: The VLSI Journal, Vol. 14, No. 3, pp. 297–332, 1993.
A. Darte and Y. Robert, “Scheduling uniform loop nests,” Tech. Rep. 92-10, ENSL Lyon, France, 1992.
W.H. Chou and S.Y. Kung, “Scheduling partitioned algorithms on processor arrays with limited communication supports,” in Proc. of Conf. on Application Specific Processor Arrays, ASAP 93, Venice, Italy, Oct. 1993, pp. 53–64.
L. Thiele, “Resource constraint scheduling of uniform algorithms,” in Proc. of Conf. on Application Specific Processor Arrays, ASAP 93, Venice, Italy, Oct. 1993, pp. 29–40.
Michèle Dion, Tanguy Risset, and Yves Robert, “Resource-constrained scheduling of partitioned algorithms on processor arrays,” Integration, the VLSI Journal, Vol. 20, pp. 139–159, 1996.
Alain Darte and Yves Robert, “Constructive methods for scheduling uniform loop nests,” IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 5, pp. 814–822, Aug. 1994.
E. Coffman, Computer and Job-Scheduling Theory, John Wiley and Sons, New York, 1976.
M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, Freeman, New York, 1976.
M. McFarland, A. Parker, and R. Camposano, “The high-level synthesis of digital system,” Proceedings of the IEEE, Vol. 78, No. 2, pp. 301–318, 1990.
C. Hwang, J. Lee, and Y. Hsu, “A formal approach to the scheduling problem in high level synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-10, No. 4, pp. 464–475, 1991.
A. Bachmann, M. Schöbinger, and L. Thiele, “Synthesis of domain specific multiprocessor systems including memory design,” in VLSI Signal Processing, IEEE Press, New York, 1993, Vol. VI, pp. 417–425.
C.H. Gebotys and M.I. Elmasry, “Global optimization approach for architectural synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-12, No. 9, pp. 1266–1278, Sept. 1993.
Y.T. Hwang and Y.H. Hu, “Novel scheduling scheme for systolic arrays,” in Proceedings of IEEE Workshop on VLSI Signal Processing, pp. 355–364, 1992.
G.L. Nemhauser and L.A. Wolsey, Integer and Combinatorial Optimization, John Wiley and Sons, New York, 1988.
S.K. Rao, Regular Iterative Algorithms and Their Implementations on Processor Arrays, Ph.D. thesis, Stanford University, 1985.
L. Thiele, “On the design of piecewise regular processor arrays,” in Proc. IEEE Symp. on Circuits and Systems, pp. 2239–2242, 1989.
L. Thiele, “CAD for signal processing architectures,” in The State of the Art in Computer Systems and Software Engineering, P. Dewilde (Ed.), Kluwer Academic Publishers, Boston, 1992.
J. Teich, A Compiler for Application-Specific Processor Arrays, Shaker (Reihe Elektrotechnik). Zugl. Saarbrücken, Univ. Diss, ISBN 3-86111-701-0, Aachen, Germany, 1993.
K.H. Zimmermann and W. Achtziger, “Finding space-time transformations for uniform recurrences via branching parametric linear programming,” Int. Journal VLSI Signal Processing, Vol. 11, 1996 (to appear).
L. Thiele, “Resource constraint scheduling of uniform algorithms,” Int. Journal VLSI Signal Processing, Vol. 10, pp. 295– 310, 1995.
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Teich, J., Thiele, L. & Zhang, L.Z. Partitioning Processor Arrays under Resource Constraints. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 17, 5–20 (1997). https://doi.org/10.1023/A:1007935215591
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DOI: https://doi.org/10.1023/A:1007935215591