Introduction

Optical computing is a striking issue in recent years. The logic gates are the fundamental devices to carry out this task1. All-optical logic gates based on photonic crystal (PC) waveguides, and ring resonators were proposed recently2,3,4. Also, there are many all-optical structures proposed to demonstrate the all-optical reservoir computing devices5,6,7,8. Thanks to the progress of the photonic technology which have been investigated intensively in recent decades, we can make these devices as a tiny chip9,10,11,12. Moreover, the temporal solitons and the continuous-wave light sources were used as the carriers of the input and output signals. The refractive index change of the waveguide by means of non-linear Kerr effect with high power light beam produces the tuning or switching of the output states of logic gates13,14. However, a long propagation path around several micrometers or even millimeters through the dielectric waveguides to deliver the light from light source to the logic gates might not be avoidable in a dielectric material (such as silicon) chip. The light might be absorbed by the waveguides leading to the deformation of the solitons. The low absorption and dispersion waveguides such as the hollow waveguide or using 3-dimensional PC structure over the waveguide might be considered to connect the light sources and the logic gates as well as to connect between the logic gates15,16,17.

Active components such as a tri-mode laser, Fabry–Perot laser, and semiconductor saturable absorber had also been proposed to form the all-optical logic gates14,18,19. Through tuning the optical injection of the tri-mode lasers, the change of logical state can be achieved14. High-speed all-optical logic gates at the bit rate of 340 Gb/s using the cross-gain modulation in semiconductor optical amplifier has also been achieved19.

Recently, researchers proposed the logic gates which are formed by microring/microdisk modulator20,21. Although the microring-/microdisk-modulators are tinier than our logic gate, the control process is more complicated than our design. With regard to the microring-modulator logic gates, they can achieve only AND, OR and XOR gates20. However, they need to modify the optical structure to carry out the corresponding function. In our study, we only need to tune the coupling ratio of the directional couplers and the phase of the phase shifter to achieve 6 logic gates at the single output port. For microdisk-modulator logic gates, the authors also can achieve OR, NOR, XNOR, XOR, AND and NAND logic gates21. However, the tunable laser providing 3 different wavelengths should be used. The size of the laser source and the external cavity to tune the wavelength might occupy several hundred square micrometers or even several square millimeters. The dimension of the integrated chip could be similar to that of our design.

In our previous work, we took advantage of the reservoir computing (RC) and unsupervised learning method optical neuron networks to establish an XOR gate5. This XOR gate with low bit error ratio was obtained by scanning the delay of optical phase shifter. In the present work, an electro-optical (EO) logic gates based on RC without the recurrent property are proposed. Obviously, it is a 2-layer-multilayer-perceptron (2-layer MLP) structure. This logic gates are composed of the optical amplifiers, directional couplers (DCs), and phase modulators (PMs). Comparing this new logic gates to our previous works, the feedback signal (the recurrent property) is removed in this new design. The switching time between 0 and 1 for the output of the gates can be shortened. In this work, the matrix inversion is performed to calculate the coupling ratio of the DCs and the phase delay of the PMs using the target output of the logic gates in the same optical configuration. The reconfigurable electro-optical OR, AND, XOR, NAND, NOR and XNOR gates formed by one optical structure are demonstrated.

Design of the 2-layer-multilayer-perceptron structure

It is known that RC system has been extensively used in the development of logic gates, waveform recognition, and rainfall prediction5,22,23,24. This system is composed of the input weight matrix \({W}^{in}\), the recurrent weight matrix \(W\), and the readout matrix \({W}^{out}\). The input matrix \({W}^{in}\) is used to scale the size of the input data to the size of the matrix W. The value of the elements in Win and W is chosen randomly. In this study, the learning is completed in a single pass-through training data. The optimal readout matrix \({W}^{out}\) is used to generate the output of the RC system.

In RC system, the neuron can be described as a function of the current input and its previous calculation result which can be expressed by25

$$X\left(n\right)=\left(1-L\right)X\left(n-1\right) +Lf\left({{\varvec{W}}}^{in}u\left(n\right)+{\varvec{W}}X(n-1)\right)$$
(1)

where the function f is the nonlinear activation function of the neuron. Usually, the hyperbolic tangent function, tanh(), is used as the nonlinear activation function to converge the output value of neuron within − 1 and 126. In this research, the non-linear function of our optical neuron is provided by the optical amplifiers. (The optical setup is shown in Fig. 1.) \(L\) is the leaky rate which is a real number from 0 to 1. However, since we do not use the recurrent property of RC in the optical neural network, L and W are set to be 1 and null, respectively producing a 2-layer MLP structure. \(u\left(n\right)\) represents the n-th input data. Thus, the reservoir activation state, \(X\left(n\right)\), is modified to \(f\left({{\varvec{W}}}^{in}u\left(n\right)\right)\). The network target output \({Y}^{target}\) is given by

Figure 1
figure 1

The optical setup of this EO logic gate. CW, DC and PM stand for the continuous wave, the 2 by 2 directional coupler, and the phase modulator. The possible recombination of the input signals A and B is (0, 0), (0, 1 V), (1 V, 0) and (1 V, 1 V). The corresponding Ytarget for the XOR gate is [0 1 1 0].

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$${Y}^{target}={W}^{out}X$$
(2)
$${W}^{out}=\left[\begin{array}{ccc}{w}_{1}& {w}_{2}& \begin{array}{cc}\dots & {w}_{M}\end{array}\end{array}\right]$$
(3)
$$X=\left[\begin{array}{c}\begin{array}{c}{X}_{1}(1)\\ {X}_{2}(1)\\ \dots \end{array}\\ {X}_{M}(1)\end{array} \begin{array}{c}\begin{array}{c}{X}_{1}(2)\\ {X}_{2}(2)\\ \dots \end{array}\\ {X}_{M}(2)\end{array}\dots \begin{array}{c}\begin{array}{c}{X}_{1}(N)\\ {X}_{2}(N)\\ \dots \end{array}\\ {X}_{M}(N)\end{array}\right]$$
(4)

In Eq. (3), M and N are the number of the neurons and the number of the input data, respectively. By collecting the training data \(X\) and the target training signals \({Y}^{target}\), the readout matrix \({W}^{out}\) can be obtained by inversing the matrix X from Eq. (2).

$${W}^{out}={Y}^{target}{X}^{-1}$$
(5)

The main feature of 2-layer MLP is the fact that the training (or the optimization) is done by dealing with the readout matrix \({W}^{out}\) using the inverse of the matrix X. As we mentioned above, once we obtain the elements of \({W}^{out}\), we could deduce the coupling ratio and phase in our DCs and PMs, respectively. This will be detailed in the next section. Through this method, we can obtain the parameters of the optical devices in this optical neural network.

Methods

Figure 1 illustrates the optical setup of our EO neural-network-based logic gates. The CW laser source at the wavelength of 1550 nm with the power of 0.1 W is launched into the DCin of our logic gate. The optical nonlinear effect of the optical fibers which connect the optical devices are ignored. This DCin with the coupling ratio of 50% is used to divide equally the input light into two light beams. The two light beams are launched into the two phase modulators (PMA and PMB in Fig. 1) individually. The half-wave voltage Vπ of the PMA and PMB is set randomly to be 1 V and 2 V, respectively. The input signals A and B are applied on the phase modulators PMA and PMB, respectively. The applied voltages are 0 or 1 V of the phase modulators to present the logic 0 and 1, respectively. PMA and PMB are connected to the directional coupler DCA. After that, the output signals of DCA are launched into DCB and DCC. DCA, DCB and DCC serve as the input matrix Win of the 2-layer MLP in which the values of the elements are chosen randomly. The coupling ratio of DCA, DCB and DCC is therefore set randomly. In our research, for the example of the XOR gate, the coupling ratios of the DCA, DCB and DCC are set randomly to be 0.56, 0.83 and 0.96, respectively.

The four outputs of the DCB and DCC are connected to the optical amplifiers A1, A2, A3 and A4, individually. The optical gain of the amplifiers is given by Go/(1 + G0P/Psat) where G0, P, Psat are the small signal power gain, the power of the input light, and the saturation output power, respectively. For all amplifiers, the small signal power gain and the saturation output power are set to be 30 dB and 30dBm, respectively. The optical amplifiers provide the non-linear function which is required for 2-layer MLP system. The complex electric field of the output light of the amplifiers A1, A2, A3 and A4 are denoted by X1, X2, X3 and X4, respectively, which are regarded as the output of the neurons. Therefore, the number of the neurons, M in Eqs. (3) and (4) is 4. In other words, an optical amplifier can be regarded as an optical neuron. The readout matrix \({W}^{out}\) is composed of the 3 phase modulators PM1, PM2 and PM3 as well as the 3 directional couplers DC1, DC2 and DC3. \({\varnothing }_{1}\), \({\varnothing }_{2}\) and \({\varnothing }_{3}\) are the phase delay of the phase modulators PM1, PM2 and PM3, respectively. \({\alpha }_{1}\), \({\alpha }_{2}\) and \({\alpha }_{3}\) are the coupling ratios of the DC1, DC2 and DC3, respectively. The general formula of the output of electric field for the phase modulator and the directional coupler can be given by Eqs. (6) and (7), respectively.

$${X}_{out}={X}_{in}{e}^{i\varnothing }$$
(6)
$$\left[\begin{array}{c}{X}_{out1}\\ {X}_{out2}\end{array}\right]=\left[\begin{array}{cc}\sqrt{1-\alpha }& i\sqrt{\alpha }\\ i\sqrt{\alpha }& \sqrt{1-\alpha }\end{array}\right]\left[\begin{array}{c}{X}_{in1}\\ {X}_{in2}\end{array}\right]$$
(7)

where \({X}_{in}\) and \({X}_{out}\) represent the complex input and output electric fields of the components, respectively. \(\varnothing\) and \(\alpha\) are the phase delay of the phase modulators and the coupling ratio of the 2 by 2 DCs, respectively. The two input lights in the directional coupler are interfered. Using Eqs. (6) and (7), the complex electric field of the output light of the whole system \({Y}^{target}\) can be derived by

$${Y}^{target}=\sqrt{1-{\alpha }_{3}}\sqrt{1-{\alpha }_{1}}{X}_{1}+\mathrm{j}\sqrt{1-{\alpha }_{3}}\sqrt{{\alpha }_{1}}{e}^{i\left({\varnothing }_{1}\right)}{X}_{2}$$
$$+j\sqrt{{\alpha }_{3}}\sqrt{1-{\alpha }_{2}}{e}^{i({\varnothing }_{3})}{X}_{3}-\sqrt{{\alpha }_{3}}\sqrt{{\alpha }_{2}}{e}^{i({\varnothing }_{2}+{\varnothing }_{3})}{X}_{4}$$
(8)

The first step of the design process is to define the gate. For example, for an XOR gate, the possible recombination of the input signals A and B are (0, 0), (0, 1 V), (1 V, 0) and (1 V, 1 V). Thus, in Eq. (4), the number of the possible recombination of the input signals, \(N\), is 4. The corresponding result \({Y}^{target}\) for the XOR gate are [0 1 1 0]. The complex electric fields X1, X2, X3 and X4 are located at the output of A1, A2, A3 and A4, respectively, as shown in Fig. 1. For each recombination of the input signals, the complex values of X1, X2, X3 and X4 are collected to form the 4 by 4 matrix X of Eq. (4). According to Eq. (5), the values of \({w}_{1}\), \({w}_{2}\), \({w}_{3}\) and \({w}_{4}\) of the 1 by 4 matrix \({W}^{out}\) can be obtained using Ytarget and X. The coefficients of the terms X1, X2, X3 and X4 in Eq. (8) are equal to the 4 complex values \({w}_{1}\), \({w}_{2}\), \({w}_{3}\) and \({w}_{4}\) of \({W}^{out}\) forming 4 simultaneous equations. The phases of the complex numbers \({w}_{1}\), \({w}_{2}\), \({w}_{3}\) and \({w}_{4}\) are denoted by \({\theta }_{1}\), \({\theta }_{2}\), \({\theta }_{3}\) and \({\theta }_{4}\). The boundary conditions for \({\alpha }_{1}\), \({\alpha }_{2}\), \({\alpha }_{3}\), are real numbers between 0 and 1. By solving the simultaneous equations, \({\alpha }_{1}\), \({\alpha }_{2}\), \({\alpha }_{3}\), \({\varnothing }_{1}\), \({\varnothing }_{2}\) and \({\varnothing }_{3}\) can be obtained by

$${\alpha }_{1}=\frac{1}{1-{\left[{\frac{{w}_{1}}{{w}_{2}}e}^{i\left({\varnothing }_{1}\right)}\right]}^{2}}$$
(9)
$${\alpha }_{2}=\frac{1}{1-{\left[{\frac{{w}_{3}}{{w}_{4}}e}^{i\left({\varnothing }_{2}\right)}\right]}^{2}}$$
(10)
$${\alpha }_{3}=\frac{\left(1-{\alpha }_{1}\right){e}^{2i\left(-{\varnothing }_{2}-{\varnothing }_{3}\right)}}{\left(1-{\alpha }_{1}\right){e}^{2i\left(-{\varnothing }_{2}-{\varnothing }_{3}\right)}+{\left[\frac{{w}_{1}}{{w}_{4}}\right]}^{2}{\alpha }_{2}}$$
(11)
$${\varnothing }_{1}={\theta }_{2}-\frac{\pi }{2}$$
(12)
$${\varnothing }_{2}={\theta }_{4}-{\theta }_{3}-\frac{\pi }{2}$$
(13)
$${\varnothing }_{3}={\theta }_{3}-\frac{\pi }{2}$$
(14)

Results and discussion

The \({Y}^{target}\) for the OR, AND, XOR, NAND, NOR, XNOR logic gates is [0 1 1 1], [0 0 0 1], [0 1 1 0], [1 1 1 0], [1 0 0 0] and [1 0 0 1], respectively. For each gate, the coupling ratios of the DCA, DCB and DCC in Fig. 1, αA, αB and αC, are chosen randomly for 100 times to obtain the best tolerance. The detail calculation of tolerance will be discussed in the next section. The obtained αA, αB and αC for each gate are listed in Table 1. The corresponding coupling ratio of the directional couplers DC1, DC2, DC3 and the phase delay of the phase modulators PM1, PM2, PM3 calculated through Eqs. (2)–(14) are listed in Table 2. The output powers of the OR, AND, XOR, NAND, NOR and XNOR logic gates for different input signals A and B are shown in Fig. 2. For the electro-optical logic gates, the relation between the input signals and the output of the 2-layer MLP system follows the truth table of the corresponding logic gates. The reconfigurable logic gate can be achieved by tuning the parameters of the directional couplers27,28,29,30 and phase modulators31 as listed in Tables 1 and 2. It is worth mentioning that the phase delay of the phase modulators for NOR gate is close to null revealing that the phase modulators PM1, PM2 and PM3 might be removed. For the other gates, it is might be possible to find the solution to remove the phase modulators.

Table 1 The coupling ratio of the directional coupler DCA, DCB and DCC.
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Table 2 The coupling ratio of the directional coupler DC1, DC2 and DC3 and the phase delay of the phase modulators PM1, PM2 and PM3.
Full size table
Figure 2
figure 2

The output power of (a) OR, (b) AND, (c) XOR, (d) NAND, (e) NOR and (f) XNOR logic gates.

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We use the visibility of the output signals of logic 0 and logic 1 to evaluate the tolerance of our logic gates. The definition of visibility is shown in Eq. (15)32

$$V=\frac{{I}_{min}^{1}-{I}_{max}^{0}}{{I}_{min}^{1}+{I}_{max}^{0}}$$
(15)

where \({I}_{min}^{1}\) and \({I}_{max}^{0}\) are the minimum light intensity of the high level (logic 1) and the maximum light intensity of the low level (logic 0), respectively. For example, for the output logic of XOR gate [0 1 1 0], if the output intensity of the 2-layer MLP system is [0.001, 0.013, 0.011, 0.002], we choose \({I}_{min}^{1}\) and \({I}_{max}^{0}\) as 0.011 and 0.002, respectively to calculate the visibility.

Since the coupling ratio of the directional couplers DC1, DC2, DC3 and the phase delay of the phase modulators PM1, PM2, PM3 are solved using Eqs. (2)–(14), the light intensity of the low level (logic 0) is null. The corresponding visibility of the output signals for all logic gates is unity.

During the fabrication of the directional couplers by optical fibers or by silicon waveguides, 1% error of the coupling ratio may happen. During the operation of the phase modulators by applying the voltage on the device, 1% error of the phase delay may occur. We calculate the visibility of the output signals as the coupling ratio of DC1, DC2, DC3 and the phase delay of the phase modulators PM1, PM2, PM3 are increased with 1% error. For example, for XOR gate, α1 obtained from Eq. (9) is 49% as listed in Table 2. As α1 is increased from 49 to 50% (αA, αB, αC, α2, α3, ϕ1, ϕ2 and ϕ3 are left unchanged as listed in Tables 1 and 2), the visibility of the output signal is calculated to be 0.99. For another example, for the XOR gate, as ϕ1 is increased from 8.88° to 12.48° (increasing 3.6° = 1% from – π to π), the visibility of the output signals is 0.91. For 100 calculations of different αA, αB, αC of each gates, the highest visibility of the 2-layer MLP system for all logic gates due to 1% error of the devices is listed in Table 3.

Table 3 The visibility of the output signals for 1% error of coupling ratio of the directional couplers DC1, DC2, and DC3 as well as the phase delay of the phase modulators PM1, PM2, PM3.
Full size table

We can observe that for 1% error of the coupling ratio of the directional couplers DC1, DC2 and DC3, the worst visibility is 0.98. For 1% error of the phase delay of the phase modulators PM1, PM2 and PM3, the worst visibility is 0.83. It seems that the results could be acceptable showing that the reconfigurable optical logic gates can be achieved even with the fabrication or operation errors. In electronics, a flip-flop or latch is a circuit that can be used to store state information with a pair of cross-coupled NOR of NAND gates. The further application of the reconfigurable optical logic gates is to build the flip-flop. The optical memory could be realized.

Conclusion

In this work, we successfully establish an optical structure which can achieve EO logic gates. Thanks to this 2-layer-MLP structure, we can carry out the OR, AND, XOR, NAND, NOR and XNOR logic gates. In other words, we could take advantage of one optical neural network to achieve the most basic logic gates in optical approach. According to Eq. (5), we obtain the coupling ratio of the directional couplers DC1, DC2, and DC3 and the phase delay of the phase modulators PM1, PM2, PM3 under the ideal condition. The tolerance of the optical devices in our optical neural network is studied. The visibility changes of the output signals due to the 1% error during the fabrication and operation of the optical devices could be acceptable indicating that the reconfigurable optical logic gates can be realized in one optical configuration. Comparing our EO logic gates to the conventional electric logic gates, this EO logic gates have the capability of higher operating frequency, and high speed. In our study, the logic-gates functions among OR, AND, XOR, NAND, NOR and XNOR can be designed when the PMs and the coupling ratio of DCs are tuned in this EO logic gates. Thus, the control process is simpler. The present design uses the neural networks without recurrent property. The calculation performance could be faster than that of the previous work5. The optical logic gates can be applied to build an optical memory using the latch structure to store the information.