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Three-dimensional integration of silicon-on-insulator RF amplifier

Three-dimensional integration of silicon-on-insulator RF amplifier

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An RF amplifier implemented by wafer-scale three-dimensional integration of three completely fabricated silicon-on-insulator wafers is demonstrated. The MOSFETs are on the top and bottom tier with middle-tier matching circuits. Measured amplifier performance agrees well with simulation and the footprint is approximately 40% smaller than the conventional 2D layout.

References

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      • Chen, C.L., Wyatt, P.W., Chen, C.K., Knecht, J.M., Yost, D.-R.: `Impact of gate resistance on RF performance of fully depeleted SOI MOSFET', Proc. IEEE Top. Meet. on Silicon Monolithic Integrated Circuits in RF Systems, 2006, San Diego, CA, USA, p. 320–323.
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