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Area scaling analysis of CMOS ADCs

Area scaling analysis of CMOS ADCs

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Recently, the continuing reduction of analogue-to-digital converter (ADC) power consumption has received a lot of attention in the literature, while it is often assumed that converter area does not scale well anymore. An area scaling analysis based on historical data is performed. It is shown that ADC area scaling has been alive and well across all ADC topologies, and for both matching and noise-limited ADCs.

Inspec keywords: network topology; analogue-digital conversion; CMOS integrated circuits; power consumption

Other keywords: area scaling analysis; matching ADC; power consumption; ADC topologies; noise-limited ADC; CMOS ADC; ADC area scaling; analogue-to-digital converter

Subjects: Network topology; CMOS integrated circuits; A/D and D/A convertors; A/D and D/A convertors

References

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      • Dautriche, P.: `Analog design trends and challenges in 28 and 20 nm CMOS technology', Proc. ESSCIRC, 2011, Helsinki, Finland, p. 1–4.
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      • B. Murmann . ADC Performance Survey 1997–2012.
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      • Chiu, Y., Nikolic, B., Gray, P.R.: `Scaling of analog-to-digital converters into ultra-deep-submicron CMOS', Proc. of the IEEE Custom Integrated Circuits Conf., 2005, San Jose, CA, USA, p. 375–382.
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      • Jonsson, B.E.: `Area efficiency of ADC architectures', European Conf. on Circuit Theory and Design, 2011, Linkoping, Sweden, p. 560–563.
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