Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

A Schottky barrier cylindrical gate all around (CGAA) metal–oxide–semiconductor field-effect transistor (MOSFET) with metal source/drain (S/D) instead of the usual highly doped S/D is an excellent candidate for low power, high speed and extremely scaled MOS devices in the nano regime [1]. It offers low S/D interface contact resistivity for metallic S/D compared with doped S/D [2]. It solves the major bottlenecks of device scaling such as a very shallow S/D junction, difficult doping techniques, and a thermal budget which makes it a futuristic alternative for next-generation MOS device [3, 4]. Furthermore, the lightly doped (N_a ≤ 10¹⁶ cm⁻³) SB-CGAA device alleviates problems such as mobility degradation and random dopant fluctuation [5]. For the formation of the high-k dielectric, low-temperature processing is very important. Therefore, the SB-CGAA MOSFET is best suited as it requires low-temperature processing [6].

Long-term reliability of these nanoscale devices is also an important issue. However, undoped SB-CGAA MOSFET shows excellent immunity to short channel effects (SCEs) but the localized charges/interface trap charges at the Si–SiO₂ interface causes the threshold voltage and subthreshold slope (SS) degradation [7, 8]. The increased density of integration of these nanoscale devices on integrated circuits raises the possibility of the generation of interface trap charges. These localized charges are created either during the manufacturing process (stress-induced damage, radiation-induced damage) or by hot carriers, under high applied drain voltage near the drain-channel junction, giving rise to localized charge pile up of interface traps (N_it) near the drain-channel region [9]. In particular, these generated localized trap charges due to high electric field (leading to hot carrier generation) results in threshold voltage shift, and SS degradation by surpassing the barrier at the Si–SiO₂ interface and will disintegrate the original performance of the device and finally lead to permanent device failure [10, 11]. Previously the hot carrier degradation (HCD) mechanism based on Si–Si, Si–O and Si–H bond breaking has been thoroughly studied [12–14].

To understand the physics of SB-CGAA MOSFETs a few models have been reported [15, 16] but all of them neglected the impact of localized charges/interface charges. This work concentrates on developing the model for SB-CGAA MOSFETs to explore the effect of +/ interface trap charge (ITC, N_it) generated under hot carrier stress. Gate material engineering (GME) is a well-explored technique to mitigate the hot carrier effects (HCEs) which enhances the carrier transport efficiency by suppressing the effect of N_it [17–19]. In GME the work function of gate metal towards the drain side is lower than the gate metal work-function at the source side. A dual metal gate architecture is employed to reduce the electric field at the drain side to evaluate the effect of N_it on GME.

A two-dimensional (2D) threshold voltage model using the superposition technique has been developed. For the derivation of surface potential and V_th, 1D Poisson's and 2D Laplace equations have been solved. Finally, an analytical model is developed to model the behaviour of N_it with the incorporation of dual metal gate (DMG or GME) architecture. Developed model results are compared with the results obtained from the ATLAS-3D simulations and a close agreement is observed and is useful for designing low power, high-speed and high-frequency devices and charge trap memory devices. SB-CGAA MOSFET calibration and enhanced analog/RF performance of the DMG-SB-CGAA MOSFET over a single metal gate (SMG) SB-CGAA MOSFET has been shown in our previous work [20].

The developed model concentrates on the predictive subthreshold behaviour for a GME-SB-GAA MOSFET. For the developed model the device channel length and radius are restricted up to 40 nm and 10 nm, respectively. Quantum mechanical effects due to energy confinement are prominent in  devices with channel length much shorter than 30 nm and radius of 5 nm regime [21–23], so in the present analysis, this aspect is neglected.

Figure 1 shows a 3D and cross-sectional view of the GME-SB-CGAA MOSFET. The structure has two different work-functions of the metal gate, M₁ towards the source side with work-function ΦM₁, and M₂ towards the drain side with work-function ΦM₂ with the gate lengths L₀ and L₁, respectively.

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The silicon channel is lightly doped (N_A = 10¹⁶ cm⁻³) with device channel length (L) 40 nm, radius R = 10 nm, gate oxide thickness t_ox = 3 nm, SiO₂ permittivity ε_ox = 3.9, gate metal work-function Φ_M1 = 4.8 eV, Φ_M2 = 4.4 eV, metal S/D work-function Φ_S/D = 4.1 eV. The Shockley–Read–Hall (SRH) recombination model with concentration dependent lifetime is used to account for minority carrier recombination. The Boltzman transport model is used as a drift-diffusion model. The carrier-carrier scattering mobility model (CCSMOB), concentration dependent mobility model (CONMOB) along with Lombardi CVT (constant voltage and temperature) mobility model are used because they consider large temperature range with parallel and perpendicular field dependent mobility. The ATLAS-3D simulator has been used for numerical simulations [24]. Martin et al have shown the validity of the Atlas/Silvaco device simulator by comparing their Monte Carlo device simulation results with ALTAS-3D simulation results for Schottky barrier MOSFETs with excellent agreement [25].

3.1. Surface potential modeling

The silicon under the gate is assumed to be fully depleted. Channel potential including channel mobile carrier density is governed by Poisson's equation in two different regions and is given as

$$\begin{eqnarray}&&\displaystyle \frac{1}{r}\displaystyle \frac{\partial }{\partial r}\left(r\displaystyle \frac{\partial }{\partial r}{{\rm{\Psi }}}_{i}(r,z)\right)+\displaystyle \frac{{\partial }^{2}}{\partial {z}^{2}}{{\rm{\Psi }}}_{i}(r,z)=\displaystyle \frac{q{{N}}_{{\rm{A}}}}{{\varepsilon }_{{\rm{S}}{\rm{i}}}}\end{eqnarray} \tag{ 1 }$$

Here ψ_i(r, z) is the potential distribution in the silicon film, q is the electron charge, ε_Si is the permittivity of silicon, i = 1 and 2 shows the undamaged (region 1) and damaged (region 2) regions, respectively. N_A is the doping of silicon film.

For nanowire devices, the oxidation process during fabrication is done at high temperature (∼900 °C) under a precise clean room environment. Consequently very fine oxide is grown [26] with the least number of interface trap charges (∼1 × 10¹⁵ m⁻²), which is negligible [27]. So the impact of interface trap charges at the source side will be negligible on drain current characteristics. At the drain side however, induced hot carriers will increase the interface charge concentration (∼1 to 5 × 10¹⁶ m⁻²) and it will no more be negligible [9–11, 28]. So we consider separate flat band voltage for two regions which are written as

$$\begin{eqnarray}&&{V}_{{\rm{F}}{\rm{B}}1}={\rm{\Phi }}{M}_{1}-{{\rm{\Phi }}}_{{\rm{Si}}};\,i=1,\,0\leqslant z\leqslant {L}_{0}\end{eqnarray} \tag{ 2 }$$

$$\begin{eqnarray}&&{V}_{{\rm{F}}{\rm{B}}2}={\rm{\Phi }}{M}_{2}-{{\rm{\Phi }}}_{{\rm{Si}}}\,\pm \left(\frac{q{N}_{{\rm{i}}{\rm{t}}}}{{C}_{{\rm{o}}{\rm{x}}}}\right);i=2,\,{L}_{0}\leqslant z\leqslant ({L}_{0}+{L}_{1})\end{eqnarray} \tag{ 3 }$$

where N_it is the density of the localized charge/interface trap, Φ_Si is the silicon work-function and C_ox is the gate oxide capacitance per unit area of the GME-SB-CGAA MOSFET and is given as

$$\begin{eqnarray}&&{C}_{{\rm{o}}{\rm{x}}}=2{\varepsilon }_{{\rm{o}}{\rm{x}}}{\left({t}_{{\rm{S}}{\rm{i}}}\mathrm{ln}\left(1+\displaystyle \frac{2{t}_{{\rm{o}}{\rm{x}}}}{{t}_{{\rm{Si}}}}\right)\right)}^{-1}\end{eqnarray} \tag{ 4 }$$

and

$$\begin{eqnarray}&&{{\rm{\Phi }}}_{{\rm{Si}}}=\chi +({E}_{g}/2)-q{{\rm{\Phi }}}_{{\rm{F}}}\end{eqnarray} \tag{ 5 }$$

where χ is the electron affinity of silicon, E_g is the energy band gap and Φ_F is the Fermi potential. It can be noted that apart from different interface charge in the two regions, gate metal work-functions will also differ (ΦM₁ in undamaged and ΦM₂ in the damaged region) and this is taken into account in equations (2) and (3). By using the superposition technique, the solution of electrostatic potential ψ_i(r, z) can be decomposed into two components: the long channel solution V_i(r) and short channel solution U_i(r, z), where V_i(r) and U_i(r, z) are the solutions of the 1D Poisson equation and 2D Laplace equation, respectively. Then the electrostatic potential in a SB-CGAA MOSFET can be written as

$$\begin{eqnarray}&&{{\rm{\Psi }}}_{i}(r,z)={V}_{i}(r)+{U}_{i}(r,z)\end{eqnarray} \tag{ 6 }$$

Equation (1) is then decomposed into equations (7) and (8) as

$$\begin{eqnarray}&&\displaystyle \frac{1}{r}\displaystyle \frac{\partial {V}_{i}(r)}{\partial r}+\displaystyle \frac{{\partial }^{2}{V}_{i}(r)}{\partial {r}^{2}}=\displaystyle \frac{q{N}_{a}}{{\varepsilon }_{si}}\end{eqnarray} \tag{ 7 }$$

$$\begin{eqnarray}&&\displaystyle \frac{1}{r}\displaystyle \frac{\partial {U}_{i}(r,z)}{\partial r}+\displaystyle \frac{{\partial }^{2}{U}_{i}(r,z)}{\partial {r}^{2}}+\displaystyle \frac{{\partial }^{2}{U}_{i}(r,z)}{\partial {z}^{2}}=0\end{eqnarray} \tag{ 8 }$$

where i = 1 for the undamaged region (with Φ_M1) and i = 2 for the damaged region (with Φ_M2). 1D potential V_i(r) can be obtained by solving Poisson's equation with the following boundary conditions:

• a.  
  Potential at the centre of the silicon pillar is ψ_c,

  $$\begin{eqnarray}&&{{\rm{\Psi }}}_{i}(r=0,z)={{\rm{\Psi }}}_{{\rm{c}}}(z)\end{eqnarray} \tag{ 9a }$$
• b.  
  Electric flux at the centre of the silicon pillar is zero,

  $$\begin{eqnarray}&&\displaystyle \frac{\partial }{\partial r}{{\rm{\Psi }}}_{i}(r=0)=0\end{eqnarray} \tag{ 9b }$$
• c.  
  Potential at the surface of the silicon pillar

  $$\begin{eqnarray}&&{{{\rm{\Psi }}}_{{i}}(r,z)| }_{r=\displaystyle \frac{{t}_{{\rm{\text{Si}}}}}{2}}={{\rm{\Psi }}}_{{S}}\left(r=\displaystyle \frac{{t}_{{\rm{\text{Si}}}}}{2},z\right)\end{eqnarray} \tag{ 9c }$$
• d.  
  Electric flux at the surface of the silicon pillar is continuous

$$\begin{eqnarray}&&{\left.\displaystyle \frac{\partial }{\partial r}{{\rm{\Psi }}}_{{i}}(r,z)\right|}_{r=\displaystyle \frac{{t}_{{\rm{\text{Si}}}}}{2}}=\displaystyle \frac{{C}_{{\rm{\text{ox}}}}}{{\varepsilon }_{{\rm{\text{Si}}}}}\left[{V}_{{\rm{G}}{\rm{S}}}-{V}_{{\rm{F}}{\rm{B}}{\rm{i}}}-{{\rm{\Psi }}}_{{i}}\left(r=\displaystyle \frac{{t}_{{\rm{\text{Si}}}}}{2},z\right)\right]\end{eqnarray} \tag{ 9d }$$

The solution of 1D Poisson equation (7) using the boundary conditions given in (9a)–(9d) can be expressed as

$$\begin{eqnarray}&&{V}_{1}(r)=\displaystyle \frac{q{N}_{a}}{4{\varepsilon }_{{\rm{\text{Si}}}}}{r}^{2}+{V}_{{\rm{\text{GS}}}}-{V}_{{\rm{F}}{\rm{B}}1}-\displaystyle \frac{q{N}_{a}{t}_{{\rm{\text{Si}}}}^{2}}{16{\varepsilon }_{{\rm{\text{Si}}}}}-\displaystyle \frac{q{N}_{a}{t}_{{\rm{\text{Si}}}}}{4\beta {\varepsilon }_{{\rm{\text{Si}}}}}\end{eqnarray} \tag{ 10a }$$

and

$$\begin{eqnarray}&&{V}_{2}(r)=\displaystyle \frac{q{N}_{a}}{4{\varepsilon }_{{\rm{S}}{\rm{i}}}}{r}^{2}+{V}_{{\rm{G}}{\rm{S}}}-{V}_{{\rm{F}}{\rm{B}}2}-\displaystyle \frac{q{N}_{a}{t}_{{\rm{S}}{\rm{i}}}^{2}}{16{\varepsilon }_{{\rm{S}}{\rm{i}}}}-\displaystyle \frac{q{N}_{a}{t}_{{\rm{S}}{\rm{i}}}}{4\beta {\varepsilon }_{{\rm{S}}{\rm{i}}}}\end{eqnarray} \tag{ 10b }$$

Here V_GS is the gate-to-source voltage; t_Si is the diameter of the silicon pillar and β = C_ox/ε_Si. The solution of 2D Laplace equation (8) can be obtained using the following boundary conditions:

• a.  
  At the interface of two different metal gates, potential is continuous

  $$\begin{eqnarray}&&{{{\rm{\Psi }}}_{1}(r,z)| }_{z={L}_{0}}={{{\rm{\Psi }}}_{2}(r,z)| }_{z={L}_{0}}\end{eqnarray} \tag{ 11a }$$
• b.  
  At the interface of M₁ and M₂, electric field is continuous

$$\begin{eqnarray}&&\displaystyle \frac{\partial }{\partial z}{{{\rm{\Psi }}}_{1}(r,z)| }_{z={L}_{0}}=\displaystyle \frac{\partial }{\partial z}{{\rm{\Psi }}}_{2}{(r,z)| }_{z={L}_{0}}\end{eqnarray} \tag{ 11b }$$

• a.  
  Potential at the source end

  $$\begin{eqnarray}&&{{\rm{\Psi }}}_{i}(r,z=0)={V}_{{\rm{b}}{\rm{i}},{\rm{S}}/{\rm{D}}}-{\rm{\Delta }}{{\rm{\Phi }}}_{{\rm{b}}{\rm{S}}}\end{eqnarray} \tag{ 11c }$$
• b.  
  Potential at the drain end

$$\begin{eqnarray}&&{{\rm{\Psi }}}_{i}(r,z={L}_{0}+{L}_{1})={V}_{{\rm{b}}{\rm{i}},{\rm{S}}/{\rm{D}}}-{\rm{\Delta }}{{\rm{\Phi }}}_{{\rm{b}}{\rm{D}}}+{V}_{{\rm{D}}{\rm{S}}}\end{eqnarray} \tag{ 11d }$$

Here V_bi,S/D is the built-in potential at the S/D, ΔΦ_bS and ΔΦ_bD are SB lowering at the source and drain, respectively [29, 30] and can be expressed as

$$\begin{eqnarray}&&{V}_{{\rm{b}}{\rm{i}},{\rm{S}}/{\rm{D}}}={{\rm{\Phi }}}_{{\rm{S}}{\rm{i}}}-{{\rm{\Phi }}}_{{\rm{S}}/{\rm{D}}}\end{eqnarray} \tag{ 12 }$$

$$\begin{eqnarray}&&{\rm{\Delta }}{{\rm{\Phi }}}_{{\rm{b}}{\rm{S}}}=\alpha {\left[\displaystyle \frac{\tau q}{4\pi {\varepsilon }_{S}}\right]}^{\displaystyle \frac{1}{2}}{{E}_{{\rm{S}}}}^{\displaystyle \frac{1}{2}}\end{eqnarray} \tag{ 13a }$$

$$\begin{eqnarray}&&{\rm{\Delta }}{{\rm{\Phi }}}_{{\rm{b}}{\rm{D}}}=\alpha {\left[\displaystyle \frac{\tau q}{4\pi {\varepsilon }_{S}}\right]}^{\displaystyle \frac{1}{2}}{{E}_{{\rm{D}}}}^{\displaystyle \frac{1}{2}}\end{eqnarray} \tag{ 13b }$$

Here χ is the electron affinity of silicon, ε_Si is the silicon permittivity, E_S and E_D are the electric fields at the source and drain end, respectively. α and τ are treated as fitting parameters (α = 1, τ = 1.1) [24].

The solution of equation (8) using the above boundary conditions can be expressed as

$$\begin{eqnarray}&&{U}_{1}(r,z)=\displaystyle \sum _{n=1}^{\infty }{J}_{0}({\Upsilon }_{n}r)({\rm A}{{\rm{e}}}^{{\Upsilon }_{n}z}+{\rm B}{{\rm{e}}}^{-{\Upsilon }_{n}z})\end{eqnarray} \tag{ 14a }$$

and

$$\begin{eqnarray}&&{U}_{2}(r,z)=\displaystyle \sum _{n=1}^{\infty }{J}_{0}({\Upsilon }_{n}r)(C{{\rm{e}}}^{{\Upsilon }_{n}z}+D{{\rm{e}}}^{-{\Upsilon }_{n}z})\end{eqnarray} \tag{ 14b }$$

A, B, C and D are the Bessel–Fourier series coefficients and are given in appendix. ϒ_n are the eigenvalues satisfying the following equation:

$$\begin{eqnarray}&&{C}_{{\rm{o}}{\rm{x}}}{J}_{0}\left({\Upsilon }_{n}\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2}\right)-{\varepsilon }_{{\rm{s}}{\rm{i}}}{\Upsilon }_{n}{J}_{1}\left({\Upsilon }_{n}\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2}\right)=0\end{eqnarray} \tag{ 15 }$$

J₀ and J₁ are the Bessel function of order zero and one, respectively.

3.2. Threshold voltage

For DMG architecture, the position of minimum surface potential resides under the metal gate with the higher work-function. The position of minimum surface potential is obtained by equating the derivative of Ψ₁ (z) to zero and is obtained as

$$\begin{eqnarray}&&{z}_{{\rm{\min }}}=(1/2{\Upsilon }_{n})\mathrm{ln}\left(\displaystyle \frac{B}{A}\right)\end{eqnarray} \tag{ 16 }$$

Thus the value of minimum surface potential is obtained as

$$\begin{eqnarray}&&{{\rm{\Psi }}}_{{\rm{\min }}}\left(\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2},{z}_{{\rm{\min }}}\right)=2\kappa -{V}_{{\rm{F}}{\rm{B}}1}-{V}_{{\rm{F}}{\rm{B}}2}+\displaystyle \frac{q{N}_{A}{r}^{2}}{2{\varepsilon }_{{\rm{S}}{\rm{i}}}}\\ &&\,\,\,\,\,\,+\,2{J}_{0}\left({{\Upsilon }}_{n}\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2}\right)\sqrt{AB}\end{eqnarray} \tag{ 17 }$$

where A, B and $\kappa$ are given in the appendix. Quantitatively the threshold voltage (V_th) for a GAA MOSFET refers to the minimum applied voltage on the gate terminal at which the minimum inversion carrier density (Q_inv) reaches its threshold value (Q_th) required for identifying the turn-on condition [5, 31, 32]. This definition of V_th is identical to the constant-current method of measurement vastly used in numerical simulations [33]. The virtual cathode position (VCP) is basically the position of minimum surface potential along the channel direction. At the VCP, the inversion carrier density is called the minimum carrier sheet density and the mobile carriers in the inversion region are controlled by the applied gate voltage.

Q_inv is obtained by taking integration of their spatial density for the entire thickness of the channel and can be expressed as

$$\begin{eqnarray}&&{Q}_{{\rm{i}}{\rm{n}}{\rm{v}}}=2\displaystyle {\int }_{0}^{{t}_{{\rm{S}}{\rm{i}}}}{n}_{i}{{\rm{e}}}^{\displaystyle \frac{{{\rm{\Psi }}}_{i}({z}_{{\rm{\min }}},r)}{{V}_{{\rm{T}}}}}{\rm{d}}r\end{eqnarray} \tag{ 18 }$$

The value of the integral in equation (18) can be approximated by taking its value at r = t_Si/2 as

$$\begin{eqnarray}&&{Q}_{{\rm{i}}{\rm{n}}{\rm{v}}}=2{n}_{i}{e}^{\displaystyle \frac{{{\rm{\Psi }}}_{i}\left({z}_{{\rm{\min }}},\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2}\right)}{{V}_{{\rm{T}}}}}{t}_{{\rm{S}}{\rm{i}}}\end{eqnarray} \tag{ 19 }$$

On solving equation (19) with case (i) Q_inv → Q_th, and (ii) V_GS → V_th, an expression of threshold voltage can be obtained as

$$\begin{eqnarray}&&{V}_{{\rm{t}}{\rm{h}}}=\displaystyle \frac{1}{(1-{f}_{2}{f}_{3})}\left[\begin{array}{c}{V}_{{\rm{T}}}\,\mathrm{ln}\left(\displaystyle \frac{{Q}_{{\rm{t}}{\rm{h}}}}{2{n}_{i}m}\right)-{f}_{2}{f}_{3}({f}_{1}+{V}_{{\rm{b}}{\rm{i}}{\rm{S}}})\\ +{f}_{1}-{f}_{2}{f}_{4}\end{array}\right]+{V}_{{\rm{F}}{\rm{B}}1}\end{eqnarray} \tag{ 20 }$$

where f₁, f₂, f₃ and f₄, are given in the appendix.

3.3. Subthreshold slope

SS given by equation (21) is an important parameter of the subthreshold region of operation for the MOSFET, and it is generally defined as the shift in the applied gate bias i.e. V_GS required to reduce the subthreshold current by one decade. For a GME-SB-CGAA MOSFET to have an excellent turn-on characteristic, SS should be as low as possible [34]. The minimum attainable SS value for any device at room temperature is nearly 60 mV/dec. But due to the presence of interface trap density, the surface state capacitance modifies the V_FB and SS changes and increases or decreases depending upon the type of interface trap charge (ITC) (+/−). Hence it is a suitable parameter to measure the impact of the interface traps on device performance, written as

$$\begin{eqnarray}&&SS={V}_{{\rm{T}}}\,\mathrm{log}(10){\left[{\left\{\displaystyle \frac{\partial {\rm{\Psi }}\left(\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2},z\right)}{\partial {V}_{{\rm{G}}{\rm{S}}}}\right\}}^{-1}\right]}_{z={z}_{{\rm{\min }}}}\end{eqnarray} \tag{ 21 }$$

where z_min can be calculated from (16). Equation (21) shows the direct dependence of SS on z_min which is affected by N_it. So it also reflects the degradation of SS due to interface traps generated by hot carrier degradation which increases as time passes. The increase in SS slows down the device switching performance.

3.4. Subthreshold current

The total subthreshold current is due to the thermionic current and the tunneling current, given as

$$\begin{eqnarray}&&{I}_{\mathrm{Thermionic}}\\ &&\,=\pi {t}_{{\rm{S}}{\rm{i}}}ukT{n}_{i}\displaystyle \frac{\left(1-{{\rm{e}}}^{\left(\displaystyle \frac{-{V}_{{\rm{D}}{\rm{S}}}q}{kT}\right)}\right)}{\left[\displaystyle {\int }_{0}^{L}\left[\displaystyle \frac{1}{\displaystyle {\int }_{0}^{R}{\rm{e}}\left[\displaystyle \frac{({\rm{\Psi }}(r,{V}_{{\rm{D}}{\rm{S}}},{V}_{{\rm{G}}{\rm{S}}},z))}{kT}\right]{\rm{d}}r}\right]{\rm{d}}z\right]}\,\end{eqnarray} \tag{ 22 }$$

and

$$\begin{eqnarray}&&{I}_{\mathrm{Tunneling}}=\pi {{t}}_{{\rm{S}}{\rm{i}}}{A}^{* }{T}^{2}{{\rm{e}}}^{\left(\displaystyle \frac{-{\phi }_{b}}{{E}_{00}({\phi }_{b})}\right)}\left({{\rm{e}}}^{\left(\displaystyle \frac{{V}_{{\rm{g}}{\rm{s}}}q}{nkT}\right)}-1\right)\end{eqnarray} \tag{ 23 }$$

Here μ (0.13 m² V⁻¹ s⁻¹) is the mobility, n_i (1.45 × 10¹⁰ cm⁻³) is the intrinsic carrier concentration, A^* is the Richardson constant, ϕ_b is the barrier height, and E₀₀ is the constant of the material associated with the WKB expression and can be given as [35, 36]:

$$\begin{eqnarray}&&{A}^{* }=\displaystyle \frac{4\pi q{m}^{* }{k}^{2}}{{h}^{3}}\end{eqnarray} \tag{ 24 }$$

$$\begin{eqnarray}&&{E}_{00}=\alpha ({\phi }_{b})q\displaystyle \frac{\hslash }{2}\sqrt{\displaystyle \frac{{N}_{A}}{{m}^{* }{\varepsilon }_{{\rm{S}}{\rm{i}}}}}\end{eqnarray} \tag{ 25 }$$

$$\begin{eqnarray}&&\alpha ({\phi }_{b})=F+U{\phi }_{b}\end{eqnarray} \tag{ 26 }$$

Here m^*(0.26m₀) is the effective mass of the electron, and m₀ is the rest mass of the electron, k is the Boltzman constant, $\hslash =h/2\pi$ where h is the plank constant. F and U are fitting parameters with values 21.8 and 36.6 (1/eV) [23], respectively.

The total subthreshold current is the combination of both I_thermionic and I_Tunneling [37] and is given as:

$$\begin{eqnarray}&&{{I}}_{\text{Sub}\_\text{total}}=({{I}}_{{\rm{thermionic}}}{{I}}_{{\rm{Tunneling}}})/({{I}}_{{\rm{thermionic}}}+{{I}}_{{\rm{Tunneling}}})\end{eqnarray} \tag{ 27 }$$

The other unknown symbols used above are given in the appendix.

Figure 2 shows the numerical simulation of drain current variation (in the log and linear scale) with respect to gate voltage for the device including quantum effects using the Bohr quantum model (BQM) and excluding quantum effects. It can be inferred from the figure that for a device size of R = 10 nm and L = 40 nm simulated drain currents are similar with and without BQM consideration. Hence in the present analysis quantum effects have been neglected. Thus its effect on the threshold voltage can also be neglected.

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Flat band voltage (V_FB) is an important and decisive parameter for a MOSFET device while calculating threshold voltage. The presence of localized ITC in the damaged region (towards the drain) caused additional band bending, thus altering V_FB of the device [33]. Consequently, this results in threshold voltage degradation, which is a major reliability concern for low power memory devices.

Figure 3(a) shows the variation of valance band and conduction band energy profile with position along the channel at different N_it (+ve/−ve) ITC. This effect of the change in band bending due to ITC in V_FB is incorporated using equation (3). It depicts that due to the presence of ITC in the damaged region the valance and conduction band energy is raised/lowered for negative/positive localized charges. The amount of change in V_FB under the damaged region mainly relies on the oxide capacitance and the density of ITC. Figure 3(b) illustrates the variation of surface potential with position along the channel at different localized +ve/−ve ITC values. At the Si–SiO₂ interface acceptor type traps accept an electron and the damaged region acts as a negative localized charge and the donor type interface traps act as a positive localize charge [38]. The effect of N_it generated by hot carriers depends on the instantaneous bias conditions. Since ITCs are electrically linked with the underlying Si, occupation of the traps depends on the Fermi level (E_F) at the silicon and SiO₂ interface and the interface states can be respectively positively charged (donor-type), neutral, or negatively charged (acceptor-type). In particular, interface state energy level (E_it) in the band gap with respect to the Fermi level decides the type of ITC: positive (E_it > E_F) for donor-type and negative (E_it < E_F) for acceptor-type interface states [39–41].

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Hence due to negative localized charge the surface potential reduces and for positive localized charge the surface potential increases. GME devices are more immune to ITC compared to SMG MOSFETs as the variation of surface potential due to localized charges is more prominent in SMG MOSFETs [17, 18]. This is because of the low electric field with smaller metal gate work-function at the drain side in GME architecture. With the reduction of peak electric field in the channel, the carrier transport efficiency increases thus increasing the lifetime of the device.

It can be seen from the figure that even though the trap charges have been considered after the L/2 channel length and the minimum of the surface potential lies under the high metal gate work-function, the shift in potential is still clearly noticeable. This shift in potential (increase/decrease) is due to the change in flat band voltage.

Marchack et al [41] showed that the hot carrier induced localized charges are mainly prominent towards the drain side. So in the present analysis, the traps have been considered towards the drain side only and the ITC generated by radiation and stress induced damage (uniform in nature) are neglected. The effect of increasing positive trap charge density on surface potential has been shown in figure 4(a). In the case of donor type N_it, the surface potential in the damaged region rises under the lower metal gate work-function.

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With the increase in the density of positive trap charges the potential further rises and results in a shift of minimum surface potential in the channel in an upward direction. Change in minimum surface potential alters the normal threshold voltage (V_th) of a GME-SB-CGAA-MOSFET. The upward shift of the minimum surface potential results in a decrease of threshold voltage. The effect of increasing negative ITC on surface potential is shown in figure 4(b) and the lowering of the surface potential is more apparent for negative ITC. The lowering in minimum surface potential with the increase of negative ITC causes a increase of threshold voltage of the device. In the case of negative ITC, the drastic change in minimum surface potential is noticeable compared to positive ITC. In the case of Schottky barrier MOSFETs dangling bond or interface states at the metal–semiconductor interface causes an image force inside the channel and this process is called Fermi level pinning. The barrier height lowering due to this image force (defined in equation (13b)) is directly proportional to the charge under the screen gate region (region 2). And due to the nature of these interface states more lowering of surface potential in the case of negative ITC takes place. Furthermore, the device is a dual metal gate structure which has an abrupt junction at 20 nm length and there is an abrupt shift in surface potential as shown in figure 4(b). Due to the presence of localized charges in the damaged region (L ≥ 20 nm), the surface potential will shift in the downward direction. The surface potential shift directly depends on interface trap charge density and thus for higher trap charges it will shift further downward which affects the gradient of the surface potential profile at around 20 nm. The developed model shows an exact match with TCAD simulation. Figure 5(a) shows the variation of the threshold voltage for different values of –/+ ITC at different thicknesses of the gate dielectric (t_ox = 2, 3 nm). Based on the surface potential analysis of the positive/negative ITC the threshold voltage has been calculated (analytical) and is in good agreement with the simulated data.

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The change in V_th in the case of negative ITC is noticeable, whereas in the case of positive ITC for 3 nm gate dielectric thickness, V_th is less influenced by the donor type traps. Furthermore, for thinner gate oxide (t_ox = 2 nm) V_th of a GME-SB-CGAA MOSFET increases without any interface trap. This is due to the enhanced electrostatic control of the gate over the channel and the density of mobile carriers is susceptible to the gate oxide thickness at any applied V_GS (gate voltage). The low oxide thickness (2 nm) has a similar impact of ITC on V_th for negative or positive ITC due to the improved control of the gate. The change in threshold voltage at different t_ox for different –/+ ITC values is tabulated in table 1 and it renders that the impact of positive N_it is almost similar to drain induced barrier lowering (DIBL) on V_th and SS, whereas the negative N_it counters the DIBL effect.

The subthreshold behaviour of the device has great importance as it gives the amount of leakage in the device while turning the device on. Figure 5(b) shows the variation of subthreshold current of a GME-SB-CGAA MOSFET for different –/+ interface trap values. The presence of ITC changes the charge distribution in the channel and thus the flat band voltage in the damaged region changes. This leads to a change in surface potential and the threshold voltage of the device. It also degrades the subthreshold current and SS of the device. From the figure, it is clear that the negative ITC decreases the off-state current (I_off) whereas positive ITC increases the off-state current (I_off). The GME-SB-CGAA MOSFET is a lightly doped device and hence it offers reduced carrier mobility degradation. Therefore no substantial change in the on-current of the device takes place.

However, the increase (decrease) in I_off due to positive (negative) ITC will definitely change the I_on/I_off ratio of the device and will affect the original switching performance of the device while using digital applications and thus is a major reliability issue. Figure 6(a) shows the variation of the threshold voltage at different channel length for –/+ ITC. For the ITC values of 1 × 10¹⁶ m⁻² and 3 × 10¹⁶ m⁻², negative (positive) ITC causes an increase (decrease) in threshold voltage of the device. It is clear from the figure 6(a) that negative ITC shows more influence on V_th rather than the positive ITC. As is evident from figures 4(a) and (b) the negative ITC changes the position of the minimum surface potential more effectively compared to positive ITC, thus the shift in threshold voltage is also more prominent in the case of negative ITC. Figure 6(a) shows that for a long channel device (L = 80 nm) GME-SB-CGAA MOSFET, the ITC (either positive or negative) has a minor impact on threshold voltage shift. Figure 6(b) depicts the V_th variation at different channel radius of a GME-SB-CGAA MOSFET for different (−/+) ITC. It shows that with the variation of channel radius, positive ITC leads to a minor change in V_th but for negative ITC the change in V_th is noticeable.

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Figure 7(a) shows the variation of SS without the interface trap charges for t_ox = 2 nm and 3 nm. As the device channel length increases the SS value reaches closer to the theoretical limit of SS. The SS of a GME-SB-CGAA MOSFET for t_ox = 2 nm is lower than for t_ox = 3 nm, because of increased control of the gate over the channel which offers reduced I_off. Figure 7(b) shows the SS at different channel lengths for positive ITC. As the channel length decreases the value of SS for positive ITC increases compared to the undamaged device. Figure 7(c) demonstrates the lowering of SS for the negative ITC.

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In summary, V_th, SS and the subthreshold current degradation due to the different −/+ ITC in a GME-SB-CGAA MOSFET have been extensively studied by varying the device structural parameters such as channel length, channel radius and gate dielectric thickness. An extensive physics based localized/ITC dependent subthreshold current analytical model including Schottky barrier lowering has been developed for a GME-SB-CGAA MOSFET. The analytical results are in good agreement with simulation results and it can be concluded from the overall analysis that the −/+ localized charges cause increases (decreases) in surface potential, SS and subthreshold current. However, the result shows that the device is more immune to donor type traps and the effect of traps is reduced at low values of gate dielectric.

The authors are thankful to DRDO, Ministry of Defence, Government of India (ERIP/ER/1002196/M/1395) for providing the financial support to carry out this work. One of the authors (Manoj Kumar) would like to thank UGC, Government of India for providing the necessary financial support to carry out this research work.

The coefficients of equations (14)–(20) are:

$$\begin{eqnarray*}&&m=\displaystyle \frac{{t}_{{\rm{S}}{\rm{i}}}}{2},\,\kappa ={V}_{{\rm{G}}{\rm{S}}}-\displaystyle \frac{q{N}_{A}{t}_{{\rm{S}}{\rm{i}}}^{2}}{16{\varepsilon }_{{\rm{S}}{\rm{i}}}}-\displaystyle \frac{q{N}_{A}{t}_{{\rm{S}}{\rm{i}}}}{4{\varepsilon }_{{\rm{S}}{\rm{i}}}\beta },\\ &&X={{\rm{\Phi }}}_{M1}-{{\rm{\Phi }}}_{M2}+\displaystyle \frac{q{N}_{{\rm{i}}{\rm{t}}}}{{C}_{{\rm{o}}{\rm{x}}}}\\ &&P=\displaystyle \frac{{V}_{{\rm{b}}{\rm{i}}{\rm{S}}}m{J}_{1}({\Upsilon }_{n}m)}{{\Upsilon }_{n}}-\left\{\kappa -{V}_{{\rm{F}}{\rm{B}}1}+\displaystyle \frac{q{N}_{A}{m}^{2}}{4{\varepsilon }_{{\rm{S}}{\rm{i}}}}\right\}\displaystyle \frac{m{J}_{1}({\Upsilon }_{n}m)}{{\Upsilon }_{n}}\\ &&\,\,\,+\displaystyle \frac{q{N}_{A}{m}^{2}{J}_{2}({\Upsilon }_{n}m)}{2{\varepsilon }_{{\rm{S}}{\rm{i}}}{\Upsilon }_{n}^{2}}\\ &&Q=\displaystyle \frac{({V}_{{\rm{b}}{\rm{i}}{\rm{S}}}+{V}_{{\rm{D}}{\rm{S}}})m{J}_{1}({\Upsilon }_{n}m)}{{\Upsilon }_{n}}-\left\{\kappa -{V}_{{\rm{F}}{\rm{B}}2}+\displaystyle \frac{q{N}_{A}{m}^{2}}{4{\varepsilon }_{{\rm{S}}{\rm{i}}}}\right\}\\ &&\,\,\,\,\times \displaystyle \frac{m{J}_{1}({\Upsilon }_{n}m)}{{\Upsilon }_{n}}+\displaystyle \frac{q{N}_{A}{m}^{2}{J}_{2}({\Upsilon }_{n}m)}{2{\varepsilon }_{{\rm{S}}{\rm{i}}}{\Upsilon }_{n}^{2}}\\ &&A=\displaystyle \frac{X}{{{\rm{e}}}^{{\Upsilon }_{n}{L}_{0}}m{\Upsilon }_{n}{J}_{1}({\Upsilon }_{n}m)}+\displaystyle \frac{1}{({{\rm{e}}}^{{\Upsilon }_{n}({L}_{0}+{L}_{1})}-{{\rm{e}}}^{-{\Upsilon }_{n}({L}_{0}+{L}_{1})})},\\ &&\,\,\,\times \,\left[\begin{array}{c}\displaystyle \frac{2}{{m}^{2}{J}_{1}^{2}({\Upsilon }_{n}m)}[Q-P{{\rm{e}}}^{-L{\Upsilon }_{n}({L}_{0}+{L}_{1})}]\\ +\displaystyle \frac{X{{\rm{e}}}^{-{\Upsilon }_{n}({L}_{0}+{L}_{1})}}{m{\Upsilon }_{n}{J}_{1}({\Upsilon }_{n}m)}\left[\displaystyle \frac{1}{{{\rm{e}}}^{{\Upsilon }_{n}{L}_{0}}}+\displaystyle \frac{1}{{{\rm{e}}}^{-{\Upsilon }_{n}{L}_{0}}}\right]\end{array}\right]\\ &&B=\displaystyle \frac{2P}{{m}^{2}{J}_{1}^{2}({\Upsilon }_{n}m)}-A\\ &&C=\displaystyle \frac{1}{({{\rm{e}}}^{{\Upsilon }_{n}({L}_{0}+{L}_{1})}-{{\rm{e}}}^{-{\Upsilon }_{n}({L}_{0}+{L}_{1})})}\left[\displaystyle \frac{2}{{m}^{2}{J}_{1}^{2}({\Upsilon }_{n}m)}\right.\\ &&\,\,\,\times [Q-P{{\rm{e}}}^{-{L}_{1}{\Upsilon }_{n}({L}_{0}+{L}_{1})}]+\displaystyle \frac{X{{\rm{e}}}^{-{\Upsilon }_{n}({L}_{0}+{L}_{1})}}{m{\Upsilon }_{n}{J}_{1}({\Upsilon }_{n}m)}\\ &&\,\,\,\times \left.\left[\displaystyle \frac{1}{{{\rm{e}}}^{{\Upsilon }_{n}{L}_{0}}}+\displaystyle \frac{1}{{{\rm{e}}}^{-{\Upsilon }_{n}{L}_{0}}}\right]\right]D=B-\displaystyle \frac{X}{{{\rm{e}}}^{-{\Upsilon }_{n}{L}_{0}}m{\Upsilon }_{n}J({\Upsilon }_{n}m)},\\ &&{f}_{1}=\displaystyle \frac{q{N}_{A}{t}_{{\rm{S}}{\rm{i}}}}{4{\varepsilon }_{{\rm{S}}{\rm{i}}}\beta },\,{f}_{2}=\displaystyle \frac{2{J}_{0}({\Upsilon }_{n}m)}{{a}^{2}{J}_{1}^{2}({\Upsilon }_{n}m)},\,{f}_{3}=\displaystyle \frac{a{J}_{1}({\Upsilon }_{n}m)}{{\Upsilon }_{n}},\\ &&{f}_{4}=\displaystyle \frac{q{N}_{A}{a}^{2}{J}_{2}({\Upsilon }_{n}m)}{2{\varepsilon }_{{\rm{S}}{\rm{i}}}{\Upsilon }_{n}^{2}}\end{eqnarray*}$$